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    GAIN MISMATCH CORRECTION FOR VOLTAGE-TO-DELAY PREAMPLIFIER ARRAY
    1.
    发明申请
    GAIN MISMATCH CORRECTION FOR VOLTAGE-TO-DELAY PREAMPLIFIER ARRAY 有权

    公开(公告)号：US20220209782A1

    公开(公告)日：2022-06-30

    申请号：US17133745

    申请日：2020-12-24

    Applicant: Texas Instruments Incorporated

    Inventor： Narasimhan RAJAGOPAL ,  Chirag Chandrahas SHETTY ,  Neeraj SHRIVASTAVA ,  Prasanth K ,  Eeshan MIGLANI

    IPC: H03M1/12 ,  H03L7/081 ,  H03K5/24

    Abstract: A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.

    CALIBRATION TECHNIQUE FOR CURRENT STEERING DAC
    2.
    发明申请
    CALIBRATION TECHNIQUE FOR CURRENT STEERING DAC 有权
    电流转向DAC的校准技术

    公开(公告)号：US20170041014A1

    公开(公告)日：2017-02-09

    申请号：US15048027

    申请日：2016-02-19

    Applicant: Texas Instruments Incorporated

    Inventor： Neeraj SHRIVASTAVA ,  Supreet JOSHI ,  Himanshu VARSHNEY ,  Jafar Sadique KAVILADATH ,  Visvesvaraya PENTAKOTA ,  Shagun DUSAD

    IPC: H03M1/10 ,  H03M1/74 ,  H03M1/78

    CPC classification number: H03M1/1009 ,  H03M1/1019 ,  H03M1/1057 ,  H03M1/66 ,  H03M1/742 ,  H03M1/745 ,  H03M1/785

    Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

    Abstract translation: 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。

    PIPELINED ANALOG-TO-DIGITAL CONVERTER
    4.
    发明申请
    PIPELINED ANALOG-TO-DIGITAL CONVERTER 审中-公开

    公开(公告)号：US20190296758A1

    公开(公告)日：2019-09-26

    申请号：US16358456

    申请日：2019-03-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arun MOHAN ,  Neeraj SHRIVASTAVA

    IPC: H03M1/12 ,  H03M1/38 ,  H03M1/06 ,  H03F3/04

    Abstract: An analog-to-digital converter including a first stage and a second stage. The first stage includes a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output. The first stage also includes a buffer, a first flash converter and a first digital-to-analog converter (DAC). The buffer has an input coupled to the first SH output and has a buffer output. The first flash converter has an input coupled to the first SH output, and has a first flash converter output. The first DAC has an input coupled to the first flash converter output. The second stage includes a second flash converter having an input coupled to the buffer output.

    ANALOG-TO-DIGITAL CONVERTER WITH AN OVER-RANGE STAGE
    7.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER WITH AN OVER-RANGE STAGE 有权

    公开(公告)号：US20250023575A1

    公开(公告)日：2025-01-16

    申请号：US18524652

    申请日：2023-11-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya Appala PENTAKOTA ,  Sai Vikas KANDIMALLA ,  Neeraj SHRIVASTAVA ,  Eeshan MIGLANI

    IPC: H03M1/10

    Abstract: An analog-to-digital converter (ADC) includes: a time-domain ADC core; and a calibration circuit. The time-domain ADC core includes: a first delay-to-digital stage having a terminal; a second delay-to-digital stage having a terminal; a third delay-to-digital stage having a terminal. The calibration circuitry is coupled to the terminal of the first delay-to-digital stage, the terminal of the second delay-to-digital stage, and the terminal of the third delay-to-digital stage of stages. The calibration circuitry is configured to calibrate the first delay-to-digital stage, the second delay-to-digital stage, and the third delay-to-digital stage based on a zero-crossing calibration and an over-range calibration. The over-range calibration sets a maximum threshold and a minimum threshold for the time-domain ADC relative to a reference voltage.

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