公开(公告)号：US12148828B2

公开(公告)日：2024-11-19

申请号：US17123982

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Mauricio Manfrini

IPC: H01L29/78 ,  H01L21/383 ,  H01L21/447 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate layer, a low-doping semiconductor layer, a crystalline ferroelectric layer and source and drain terminals. The crystalline ferroelectric layer is disposed between the gate layer and the low-doping semiconductor layer. The source terminal and the drain terminal are disposed on the low-doping semiconductor layer.

公开(公告)号：US12051702B2

公开(公告)日：2024-07-30

申请号：US18167776

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1248 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78675 ,  H01L29/78696 ,  H01L21/02645 ,  H01L21/02675 ,  H01L29/78618

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US11955548B2

公开(公告)日：2024-04-09

申请号：US17315687

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Chih-Yu Chang ,  Sai-Hooi Yeong

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/443 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B51/30

CPC classification number: H01L29/78391 ,  H01L21/02565 ,  H01L21/443 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869 ,  H10B51/30

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.

公开(公告)号：US20230197445A1

公开(公告)日：2023-06-22

申请号：US18167776

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/02488 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78675 ,  H01L21/02645 ,  H01L21/02675 ,  H01L29/66757 ,  H01L29/78648 ,  H01L29/78696 ,  H01L21/02532 ,  H01L21/02592

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US11569294B2

公开(公告)日：2023-01-31

申请号：US16924162

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Chung-Te Lin ,  Ken-Ichi Goto

IPC: H01L27/22 ,  H01L29/423 ,  H01L23/528 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

Abstract: A semiconductor device includes a semiconductor substrate and an interconnection region disposed on the semiconductor substrate. The interconnection region includes stacked metallization levels, a magnetic tunnel junction, and a transistor. The magnetic tunnel junction is formed on a first conductive pattern of a first metallization level of the stacked metallization levels. The transistor is formed on a second conductive pattern of a second metallization level of the stacked metallization levels. The transistor is a vertical gate-all-around transistor. A drain contact of the transistor is electrically connected to the magnetic tunnel junction by the first conductive pattern of the first metallization level. The second metallization level is closer to the semiconductor substrate than the first metallization level.

公开(公告)号：US20220223741A1

公开(公告)日：2022-07-14

申请号：US17218680

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Chang ,  Mauricio Manfrini ,  Hung Wei Li ,  Yu-Ming Lin

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/24 ,  H01L29/66

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.

公开(公告)号：US11309353B2

公开(公告)日：2022-04-19

申请号：US17078583

申请日：2020-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Ichi Goto ,  Chung-Te Lin ,  Mauricio Manfrini

IPC: H01L27/24 ,  H01L27/22

Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure comprises stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is connected to the memory cell and disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is saved, and more integration flexibility is provided.

公开(公告)号：US10971684B2

公开(公告)日：2021-04-06

申请号：US16412810

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Chung-Te Lin ,  Gerben Doornbos ,  Marcus Johannes Henricus van Dal

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

公开(公告)号：US11997855B2

公开(公告)日：2024-05-28

申请号：US17109427

申请日：2020-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Mauricio Manfrini ,  Han-Jong Chia

IPC: H10B63/00 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B63/30 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H10B61/22

Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.

公开(公告)号：US11587786B2

公开(公告)日：2023-02-21

申请号：US17224981

申请日：2021-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.