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184 条记录 (耗时 0.029 秒)

    Method of forming PZT ferroelectric capacitors for integrated circuits
    1.
    发明授权
    Method of forming PZT ferroelectric capacitors for integrated circuits 有权
    形成用于集成电路的PZT铁电电容器的方法

    公开(公告)号：US07935543B2

    公开(公告)日：2011-05-03

    申请号：US12472265

    申请日：2009-05-26

    申请人： Theodore S. Moise, IV ,  Scott R. Summerfelt ,  Kezhakkedath R. Udayakumar

    发明人： Theodore S. Moise, IV ,  Scott R. Summerfelt ,  Kezhakkedath R. Udayakumar

    IPC分类号： H01L21/00

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

    摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.

    摘要翻译： 本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到​​铁电芯的居里温度附近的温度，并对衬底进行温度程序 ，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。 本发明的实施例包括在铁电体芯上方和下方扩展横截面的金属填充通孔，其增加了在冷却期间铁电芯上的热应力。

    Ferroelectric capacitor stack etch cleaning methods
    2.
    发明授权
    Ferroelectric capacitor stack etch cleaning methods 有权
    铁电电容堆栈蚀刻清洗方法

    公开(公告)号：US07220600B2

    公开(公告)日：2007-05-22

    申请号：US11016400

    申请日：2004-12-17

    申请人： Scott R. Summerfelt ,  Lindsey H. Hall ,  Kezhakkedath R. Udayakumar ,  Theodore S. Moise, IV

    发明人： Scott R. Summerfelt ,  Lindsey H. Hall ,  Kezhakkedath R. Udayakumar ,  Theodore S. Moise, IV

    IPC分类号： H01G7/06 ,  H01L32/00

    CPC分类号： H01L21/0206 ,  H01L21/02071 ,  H01L28/55 ,  H01L28/57 ,  H01L28/65 ,  H01L28/75

    摘要： Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.

    摘要翻译： 提供了用于制造铁电电容器结构的方法（100），其包括用于在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法（128）。 所述方法包括：上电极的蚀刻（140,200）部分，蚀刻（141,201）铁电材料和蚀刻（142,202）下电极以限定图案化的铁电电容器结构，以及蚀刻（143,206）a 部分下部电极扩散阻挡结构。 所述方法还包括使用第一灰化处理灰化（144,203）所述图案化的铁电电容器结构，在第一灰化处理之后执行（145,204）湿式清洁处理，以及使用所述图案化铁电电容器结构灰化（146,205） 在氧化环境中的高温下在湿式清洁工艺之后直接进行第二次灰化处理。

    High Polarization Ferroelectric Capacitors for Integrated Circuits
    4.
    发明申请
    High Polarization Ferroelectric Capacitors for Integrated Circuits 有权
    用于集成电路的高极化铁电电容器

    公开(公告)号：US20090233382A1

    公开(公告)日：2009-09-17

    申请号：US12472265

    申请日：2009-05-26

    申请人： Theodore S. Moise, IV ,  Scott R. Summerfelt ,  K.R. Udayakumar

    发明人： Theodore S. Moise, IV ,  Scott R. Summerfelt ,  K.R. Udayakumar

    IPC分类号： H01L21/00

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

    摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.

    摘要翻译： 本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到​​铁电芯的居里温度附近的温度，并对衬底进行温度程序 ，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。 本发明的实施例包括在铁电体芯上方和下方扩展横截面的金属填充通孔，其增加了在冷却期间铁电芯上的热应力。

    Method of forming an FeRAM having a multi-layer hard mask and patterning thereof
    7.
    发明授权
    Method of forming an FeRAM having a multi-layer hard mask and patterning thereof 有权
    形成具有多层硬掩模并构图的FeRAM的方法

    公开(公告)号：US06828161B2

    公开(公告)日：2004-12-07

    申请号：US10313068

    申请日：2002-12-06

    申请人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

    发明人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L27/11507

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

    摘要翻译： 本发明涉及一种形成FeRAM集成电路的方法，其包括形成多层硬掩模。 多层硬掩模包括覆盖在蚀刻停止层上的硬掩模层。 相对于用于去除底部电极扩散阻挡层的蚀刻，蚀刻停止层比上覆掩模层更具选择性。 因此，在电容器堆叠的蚀刻期间，底部电极扩散阻挡层的蚀刻导致硬掩模层的基本上完全去除。 然而，由于蚀刻停止层相对于上覆掩模层的实质选择性（例如10:1或更多），蚀刻停止层完全保护下面的顶部电极，从而防止其暴露。

    Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier
    8.
    发明授权
    Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier 有权
    形成具有底部电极扩散阻挡层的FeRAM电容器的方法

    公开(公告)号：US06773930B2

    公开(公告)日：2004-08-10

    申请号：US10305838

    申请日：2002-11-26

    申请人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Tomojuki Sakoda ,  Chiu Chi ,  Theodore S. Moise, IV

    发明人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Tomojuki Sakoda ,  Chiu Chi ,  Theodore S. Moise, IV

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L21/28568 ,  H01L27/11507 ,  H01L28/75

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover. The TiN layer at least partially fills any seam that exists within the conductive contact, thus improving a conductivity between the FeRAM capacitor and a conductive contact in the interlayer dielectric.

    摘要翻译： 本发明涉及一种形成FeRAM集成电路的方法，其包括在FeRAM电容器堆叠中形成底部电极层之前形成TiAlON底部电极扩散阻挡层。 随后，当执行电容器堆叠蚀刻时，TiAlON扩散阻挡层中未被FeRAM电容器堆叠覆盖的部分被TiAlON扩散阻挡层内的氧基本上各向异性地蚀刻，基本上防止了其横向蚀刻。 以上述方式，防止了FeRAM电容器堆叠下的TiAlON扩散阻挡层的底切。 在本发明的另一方面，形成FeRAM电容器的方法包括形成多层底电极扩散阻挡层。 这种形成包括在层间电介质层和导电接触面上形成TiN层，并在其上形成扩散阻挡层。 TiN层至少部分地填充存在于导电接触中的任何接缝，从而提高了FeRAM电容器和层间电介质中的导电接触之间的导电性。

    Design to prevent tungsten oxidation at contact alignment in FeRAM
    9.
    发明授权
    Design to prevent tungsten oxidation at contact alignment in FeRAM 有权
    设计以防止FeRAM接触对准时的钨氧化

    公开(公告)号：US06660612B1

    公开(公告)日：2003-12-09

    申请号：US10289606

    申请日：2002-11-07

    申请人： Yung Shan Chang ,  Theodore S. Moise, IV ,  Scott R. Summerfelt

    发明人： Yung Shan Chang ,  Theodore S. Moise, IV ,  Scott R. Summerfelt

    IPC分类号： H01L2176

    CPC分类号： H01L27/11502 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/11507 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

    摘要： One aspect of the invention relates to a method of manufacturing a semiconductor device in which an alignment mark is formed by a plurality of adjacent filled trenches. A processing tool detects the trenches as though they were a single filled trench of larger dimension. When the trenches are metal filled, the metal is more easily protected from oxidation than when the metal is formed into a single large trench, an effect that is pronounced when the trenches are filled with tungsten. Another aspect of the invention relates to an alignment mark formed by a plurality of tungsten filled trenches. The alignment mark can be used to align the pattern for an FeRAM capacitor stack to underlying tungsten contacts.

    摘要翻译： 本发明的一个方面涉及一种半导体器件的制造方法，其中通过多个相邻的填充沟槽形成对准标记。 处理工具检测沟槽，好像它们是较大尺寸的单个填充沟槽。 当沟槽被金属填充时，与当金属形成单个大沟槽时相比，金属更容易被保护以免氧化，这是当沟槽被钨填充时的效果。 本发明的另一方面涉及由多个填充钨的沟槽形成的对准标记。 对准标记可用于将FeRAM电容器堆叠的图案对准下层钨触点。