公开(公告)号：US5268815A

公开(公告)日：1993-12-07

申请号：US922257

申请日：1992-07-30

申请人： Thomas M. Cipolla ,  Paul W. Coteus ,  Brian C. Derdall ,  Christina M. Knoedler ,  Alphonso P. Lanzetta ,  John J. Liutkus ,  Linda C. Matthew ,  Lawrence S. Mok ,  Irene A. Sterian

发明人： Thomas M. Cipolla ,  Paul W. Coteus ,  Brian C. Derdall ,  Christina M. Knoedler ,  Alphonso P. Lanzetta ,  John J. Liutkus ,  Linda C. Matthew ,  Lawrence S. Mok ,  Irene A. Sterian

IPC分类号： H01L25/10 ,  H05K3/30 ,  H05K7/02 ,  H05K7/20

CPC分类号： H05K7/023 ,  H01L25/105 ,  H05K3/301 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  Y10T29/53265

摘要： A high density circuit package includes a pair of planar packages, the planar packages exhibiting front and back surfaces and positioned back-to-back in the high density circuit package. Each planar package includes a flexible circuit carrier having a plurality of circuit chips mounted thereon. Front and back planar metallic heat sinks sandwich the circuit carriers, at least one of the heat sinks contacting a surface of the chips mounted on the sandwiched circuit carriers. Each heat sink is provided with air flow apertures formed in its planar surface and adjacent to each circuit chip. A circuit card interconnects with the circuit carriers in an interconnection region and is pluggable into a female connector. The planar metallic heat sinks and circuit carriers are mechanically packaged so as to provide a planar arrangement which aligns the apertures in both the front and rear heat sinks. A pair of planar packages are mechanically connected in a back-to-back arrangement so that the apertures therebetween are aligned. The associated circuit cards are also back-to-back oriented so as to enable their joint interconnection into the female connector.

摘要翻译： 高密度电路封装包括一对平面封装，平面封装呈现前后表面并且背对背设置在高密度电路封装中。 每个平面封装包括具有安装在其上的多个电路芯片的柔性电路载体。 前后平面金属散热器夹着电路载体，至少一个散热片接触安装在夹层电路载体上的芯片表面。 每个散热器设置有形成在其平面表面中并与每个电路芯片相邻的气流孔。 电路卡与互连区域中的电路载体互连，并且可插入到母连接器中。 平面金属散热器和电路载体被机械地封装，以便提供一个平面布置，其对准前后散热片中的孔。 一对平面封装以背对背布置机械连接，使得它们之间的孔对准。 相关联的电路卡也是背靠背定向的，以便使它们的连接互连到母连接器中。

公开(公告)号：US5343366A

公开(公告)日：1994-08-30

申请号：US903838

申请日：1992-06-24

申请人： Thomas M. Cipolla ,  Paul W. Coteus ,  Ioannis Damianakis ,  Glen W. Johnson ,  Peter G. Ledermann ,  Linda C. Matthew ,  Lawrence S. Mok

发明人： Thomas M. Cipolla ,  Paul W. Coteus ,  Ioannis Damianakis ,  Glen W. Johnson ,  Peter G. Ledermann ,  Linda C. Matthew ,  Lawrence S. Mok

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L25/07 ,  H05K1/14 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H01R23/68

CPC分类号： H05K3/363 ,  H01L24/01 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2225/06551 ,  H01L2225/06596 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09172 ,  H05K2201/09909 ,  H05K2201/10484 ,  H05K2201/1059 ,  H05K2201/10681 ,  H05K2201/10984 ,  H05K3/326 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/366 ,  H05K3/4007 ,  H05K3/4092

摘要： This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cuboid structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate and within which corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contain solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate surface or the pin-like structures can be adapted for insertion into apertures in a second substrate. The second substrate provides a means for electrically inter-connecting a plurality of these cuboids. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cuboid structures.

摘要翻译： 本发明涉及将集成电路芯片三维封装成堆栈以形成立方体结构。 在堆叠中的相邻芯片之间，设置有电互连装置，其是具有多个导体的第一基板，其多个导体电连接到芯片接触位置，并且其另一端延伸到芯片堆叠的一侧， 形成多个针状电互连组件。 销状结构可以由在其至少一侧上具有电导体的第一基板的凸起从该侧延伸形成。 或者，销状结构可以由从第一基板的边缘的两侧悬臂的导体形成，并且其中来自两侧的相应导体对准并且间隔开第一基板厚度。 这些空间包含焊料并形成焊料加载的针状结构。 销状结构可以直接焊接到第二衬底表面上的导体上，或者针状结构可以适于插入到第二衬底中的孔中。 第二基板提供用于电连接多个这些长方体的装置。 优选地，第一和第二基底是电路化柔性聚合物膜。 第二基板设置在诸如PC板的第三基板上，其间具有弹性材料，其允许将散热器压紧成与长方体结构的相对侧紧密接触。

公开(公告)号：US5208729A

公开(公告)日：1993-05-04

申请号：US836672

申请日：1992-02-14

申请人： Thomas M. Cipolla ,  Paul W. Coteus ,  Glen W. Johnson ,  Lawrence S. Mok

发明人： Thomas M. Cipolla ,  Paul W. Coteus ,  Glen W. Johnson ,  Lawrence S. Mok

IPC分类号： H05K5/00 ,  H01L23/467 ,  H01L25/10 ,  H05K7/14 ,  H05K7/20

CPC分类号： H05K7/1429 ,  H01L23/467 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2924/0002

摘要： A high density package for a plurality of integrated circuit chips is described, the package including a number of planar subunits. A subunit includes first and second planar metal plates and a spacer metal plate sandwiched therebetween. Each spacer metal plate is provided with a plurality of circuit-receiving apertures. A planar circuit carrier is provided for each aperture in the spacer metal plate. One face of each circuit carrier includes a plurality of bonded chips. Each circuit carrier is positioned in a circuit-receiving aperture so that rear aspects of the bonded chips bear upon the second planar metal plate. Each circuit carrier has a connector region which extends out from between the first planar metal plate and the metal spacer plate at one extremity of each circuit-receiving aperture. A circuit card is positioned at that extremity and has a plurality of interconnection areas, one for each extended connector region. The circuit card has its major surface oriented parallel to the metal plates so that the entire package presents an overall planar configuration.

公开(公告)号：US08667049B2

公开(公告)日：2014-03-04

申请号：US13566024

申请日：2012-08-03

申请人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampap ,  Philip Heidlberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

发明人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampap ,  Philip Heidlberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

IPC分类号： G06F15/173

CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

摘要翻译： 数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。 在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却​​要求的最佳平衡。 单个节点内的多个处理器单独或同时工作在要解决的特定算法所要求的计算或通信的任何组合上。 片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。 多个网络包括用于并行算法消息传递的三个高速网络，包括Torus，全局树和提供全局障碍和通知功能的全球异步网络。

公开(公告)号：US20120311299A1

公开(公告)日：2012-12-06

申请号：US13566024

申请日：2012-08-03

申请人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidlberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

发明人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidlberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

IPC分类号： G06F15/80

CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

摘要翻译： 数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。 在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却​​要求的最佳平衡。 单个节点内的多个处理器单独或同时工作在要解决的特定算法所要求的计算或通信的任何组合上。 片上系统ASIC节点通过多个独立网络进行互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。 多个网络包括用于并行算法消息传递的三个高速网络，包括Torus，全局树和提供全局障碍和通知功能的全球异步网络。

公开(公告)号：US08250133B2

公开(公告)日：2012-08-21

申请号：US12492799

申请日：2009-06-26

申请人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

发明人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

IPC分类号： G06F15/16

CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System- On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

摘要翻译： 数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。 在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却​​要求的最佳平衡。 单个节点内的多个处理器单独或同时工作在要解决的特定算法所要求的计算或通信的任何组合上。 片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。 多个网络包括用于并行算法消息传递的三个高速网络，包括Torus，全局树和提供全局障碍和通知功能的全球异步网络。

公开(公告)号：US07555566B2

公开(公告)日：2009-06-30

申请号：US10468993

申请日：2002-02-25

申请人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

发明人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

IPC分类号： G06F15/16

CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

摘要翻译： 数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即，每个处理节点包括单个专用集成电路（ASIC）。 在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却​​要求的最佳平衡。 单个节点内的多个处理器可以单独使用或同时使用，以在任何时间点解决或执行的特定算法所要求的任何计算或通信组合上工作。 片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。 在优选实施例中，多个网络包括用于并行算法消息传递的三个高速网络，包括提供全局障碍和通知功能的环形，全局树和全球异步网络。 这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。 对于特定类别的并行算法或并行计算的部分，该架构具有出色的计算性能，并且可以启用对新类并行算法执行计算。 为外部连接提供附加网络，用于输入/输出，系统管理和配置以及调试和监控功能。 实现中平面和其他硬件设备的特殊节点打包技术有助于在多个网络中划分超级计算机，以优化超级计算资源。

公开(公告)号：US20090259713A1

公开(公告)日：2009-10-15

申请号：US12492799

申请日：2009-06-26

申请人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

发明人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

IPC分类号： G06F15/76 ,  G06F15/16 ,  G06F11/28 ,  G06F12/08 ,  G06F9/02 ,  G06F15/177

CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

摘要翻译： 数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。 在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却​​要求的最佳平衡。 单个节点内的多个处理器可以单独使用或同时使用，以在任何时间点解决或执行的特定算法所要求的任何计算或通信组合上工作。 片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。 在优选实施例中，多个网络包括用于并行算法消息传递的三个高速网络，包括提供全局障碍和通知功能的环形，全局树和全球异步网络。 这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。 对于特定类别的并行算法或并行计算的部分，该架构具有出色的计算性能，并且可以启用对新类并行算法执行计算。 为外部连接提供附加网络，用于输入/输出，系统管理和配置以及调试和监控功能。 实现中平面和其他硬件设备的特殊节点打包技术有助于在多个网络中划分超级计算机，以优化超级计算资源。

公开(公告)号：US5581576A

公开(公告)日：1996-12-03

申请号：US371621

申请日：1995-01-12

申请人： Alphonso P. Lanzetta ,  Lawrence S. Mok

发明人： Alphonso P. Lanzetta ,  Lawrence S. Mok

IPC分类号： H04H20/34 ,  H04H20/86 ,  H04L5/06 ,  H04L27/00 ,  H04L27/28

CPC分类号： H04H20/34 ,  H04H20/86 ,  H04L5/06

摘要： A radio information broadcasting and receiving system consisting of three major parts: an FM transmitter station with subcarrier multiplexing capability, an FM receiver apparatus with subcarrier demodulation capability, and a computer connected in combination with the receiver apparatus. The FM transmitter station includes sources of main programming signals first digital data signals and second digital data signals. The first and second digital data signals are modulated by subcarrier 1 and subcarrier 2 frequencies respectively and are mixed with the main program signal and then transmitted. The transmitted signals are received by a receiver apparatus including an FM receiver circuit and an FM demodulator circuit for receiving the broadcast signal and demodulating it. The demodulated main program audio frequency signal is applied through a filter/deemphasis circuit and amplifier to speaker to provide an audio output. The first subcarrier frequency signal is demodulated by a first subcarrier frequency generator to provide a digital signal of the text portion of the transmitted signal which is then applied to a first input port of this digital computer. Likewise, the second subcarrier frequency is demodulated and the resultant index digital data signal is applied to a second input port of the computer.

摘要翻译： 一种无线电信息广播和接收系统，包括三个主要部分：具有子载波复用能力的FM发射机站，具有子载波解调能力的FM接收机设备，以及与接收机设备组合连接的计算机。 FM发射台包括主编程信号源，第一数字数据信号和第二数字数据信号。 第一和第二数字数据信号分别由副载波1和子载波2频率调制，并与主节目信号混合后发送。 所发送的信号由包括FM接收机电路和用于接收广播信号并对其进行解调的FM解调器电路的接收机装置接收。 解调的主程序音频信号通过滤波器/去加重电路和放大器施加到扬声器以提供音频输出。 第一副载波频率信号由第一副载波频率发生器解调，以提供发送信号的文本部分的数字信号，该数字信号然后被施加到该数字计算机的第一输入端口。 类似地，解调第二副载波频率，并将所得到的索引数字数据信号施加到计算机的第二输入端口。

公开(公告)号：US5559670A

公开(公告)日：1996-09-24

申请号：US324567

申请日：1994-10-18

申请人： Ephraim B. Flint ,  Alphonso P. Lanzetta ,  Lawrence S. Mok

发明人： Ephraim B. Flint ,  Alphonso P. Lanzetta ,  Lawrence S. Mok

IPC分类号： G06F1/16 ,  H05K5/03

CPC分类号： G06F1/1679 ,  G06F1/162 ,  G06F1/1683

摘要： The invention is a convertible display computer structure in which the display is centrally pivoted in a frame that in turn is hinged on one side on the keyboard so that the display can be positioned to face toward the user when the frame is positioned to be essentially vertical with respect to the keyboard and when it is desired to provide graphic information entry, the display can be turned over so as to serve as a writing surface when the hinged frame is positioned over the keyboard. The conversion from keyboard to graphic stylus input is accomplished by rotating the display on the pivot mountings and then closing the frame over the keyboard with the display surface up and in the proper orientation.

摘要翻译： 本发明是一种可转换显示计算机结构，其中显示器在框架中心枢转，该框架又铰接在键盘的一侧上，使得当框架被定位成基本上垂直时，显示器可以定位成面向使用者 相对于键盘，当希望提供图形信息输入时，可以翻转显示器，以便当铰链框架位于键盘上方时用作书写表面。 从键盘到图形触控笔输入的转换是通过旋转显示器在旋转安装上旋转，然后通过键盘上的显示屏面向上并以正确方向闭合框架来实现的。