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    Semiconductor structure and method for manufacturing the same
    1.
    发明授权
    Semiconductor structure and method for manufacturing the same 有权
    半导体结构及其制造方法

    公开(公告)号：US09236471B2

    公开(公告)日：2016-01-12

    申请号：US14253365

    申请日：2014-04-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

    IPC: H01L29/76 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

    Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

    Abstract translation: 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

    METHOD OF FABRICATING HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE
    2.
    发明申请
    METHOD OF FABRICATING HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE 有权
    制造高压金属氧化物半导体晶体管器件的方法

    公开(公告)号：US20150079754A1

    公开(公告)日：2015-03-19

    申请号：US14548248

    申请日：2014-11-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

    IPC: H01L29/66 ,  H01L21/033 ,  H01L29/08 ,  H01L21/266 ,  H01L29/40 ,  H01L29/06

    CPC classification number: H01L29/66681 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816

    Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.

    Abstract translation: 本发明提供一种制造HV MOS晶体管器件的方法，包括在衬底和深阱中形成深阱; 在所述深阱中形成第一掺杂区域和所述第一掺杂区域，其中所述第一掺杂区域的掺杂浓度和所述深阱在至少一个电场浓度区域中的掺杂浓度具有第一比率，所述第一掺杂区域的掺杂浓度 第一掺杂区域和电场浓度区外的深阱的掺杂浓度具有第二比例，第一比值大于第二比例; 以及在所述衬底中形成高电压阱，以及分别在所述深阱和所述高电压阱中形成第二掺杂区和第三掺杂区。

    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体结构及其制造方法

    公开(公告)号：US20140225192A1

    公开(公告)日：2014-08-14

    申请号：US14253365

    申请日：2014-04-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

    Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

    Abstract translation: 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

    Semiconductor device and method of forming the same
    6.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US08981501B2

    公开(公告)日：2015-03-17

    申请号：US13870706

    申请日：2013-04-25

    Applicant: United Microelectronics Corp.

    Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

    IPC: H01L29/84 ,  H01L21/311 ,  H01L23/48 ,  B81C1/00 ,  H01L27/06

    CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20140319693A1

    公开(公告)日：2014-10-30

    申请号：US13870706

    申请日：2013-04-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

    IPC: H01L21/311 ,  H01L23/48

    CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

    MEMS structure and method of forming the same
    10.
    发明申请
    MEMS structure and method of forming the same 有权
    MEMS结构及其形成方法

    公开(公告)号：US20140367805A1

    公开(公告)日：2014-12-18

    申请号：US13917655

    申请日：2013-06-14

    Applicant: United Microelectronics Corp.

    Inventor： Li-Che Chen ,  Te-Yuan Wu ,  Chia-Huei Lin ,  Hui-Min Wu ,  Kun-Che Hsieh ,  Kuan-Yu Wang ,  Chung-Yi Chiu

    IPC: B81C1/00

    CPC classification number: B81B3/0075 ,  B81B2207/07 ,  B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

    Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.

    Abstract translation: 一种形成MEMS结构的方法，其中形成蚀刻停止层以埋入介电层内，并且在从背面蚀刻基板和介电层之间形成室时，蚀刻停止层 保护剩余的介电层。 如此形成的室在基板的背面具有开口，与开口相对的天花板和连接天花板的侧壁。 侧壁还可包括蚀刻停止层的一部分。

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