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    Method of producing a memory cell configuration
    2.
    发明授权
    Method of producing a memory cell configuration 失效
    产生存储单元配置的方法

    公开(公告)号：US06180458B2

    公开(公告)日：2001-01-30

    申请号：US09095260

    申请日：1998-06-10

    申请人： Wolfgang Krautschneider ,  Franz Hofmann ,  Wolfgang Roesner

    发明人： Wolfgang Krautschneider ,  Franz Hofmann ,  Wolfgang Roesner

    IPC分类号： H01L21336

    CPC分类号： H01L27/1128 ,  H01L27/112

    摘要： A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F2, where F is the minimum structure size.

    摘要翻译： 存储单元配置包括具有平面MOS晶体管的第一存储单元和具有垂直MOS晶体管的第二存储单元。 平面MOS晶体管设置在平行的带状沟槽的底部和顶部上。 垂直MOS晶体管设置在沟槽的侧壁上。 存储单元配置可以用1 F2的每个存储单元的平均面积要求来生成，其中F是最小结构尺寸。

    DRAM cell arrangement and method for its manufacture
    3.
    发明授权
    DRAM cell arrangement and method for its manufacture 失效
    DRAM单元布置及其制造方法

    公开(公告)号：US5736761A

    公开(公告)日：1998-04-07

    申请号：US645503

    申请日：1996-05-14

    申请人： Lothar Risch ,  Franz Hofmann ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    发明人： Lothar Risch ,  Franz Hofmann ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10876 ,  H01L27/10823

    摘要： The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.

    摘要翻译： DRAM单元布置对每个存储单元具有一个垂直MOS晶体管，其第一源极/漏极区域邻接沟槽位线（5），其栅极电极（13）与沟槽字线连接，并且其第二源极/漏极区域（3）邻接 基板主表面（1）。 至少在第二源极/漏极区域上布置有特别是铁电体或者顺电层的电容器电介质（16），并且电容器板（17）布置在电介质上，使得第二源极/漏极区域 3）另外作为存储器节点。 可以利用4F2的存储单元表面来制造DRAM单元布置。

    Method for manufacturing an integrated circuit arrangement having at least one MOS transistor
    4.
    发明授权
    Method for manufacturing an integrated circuit arrangement having at least one MOS transistor 有权
    一种用于制造具有至少一个MOS晶体管的集成电路装置的方法

    公开(公告)号：US06274431B1

    公开(公告)日：2001-08-14

    申请号：US09301108

    申请日：1999-04-28

    申请人： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

    发明人： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

    IPC分类号： H01L2976

    CPC分类号： H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66666

    摘要： An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

    摘要翻译： 集成电路装置包含由绝缘结构围绕的MOS晶体管，其源极和漏极横向排列并且在不同的深度。 其通道基本上垂直于电路装置的表面。 由于通过蚀刻或通过生长层来确定沟道长度，所以可以实现短于小于50nm的沟道长度。 为了制造，采用其中集成平面晶体管的传统电路布置的大多数掩模，这显着地有助于结合到半导体制造中。

    DRAM cell arrangement and method for its production
    6.
    发明授权
    DRAM cell arrangement and method for its production 有权
    DRAM单元布置及其生产方法

    公开(公告)号：US6147376A

    公开(公告)日：2000-11-14

    申请号：US228611

    申请日：1999-01-12

    申请人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    发明人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

    摘要翻译： 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。

    Method for DRAM cell arrangement and method for its production
    7.
    发明授权
    Method for DRAM cell arrangement and method for its production 有权
    DRAM单元布置方法及其制作方法

    公开(公告)号：US06184045B2

    公开(公告)日：2001-02-06

    申请号：US09541952

    申请日：2000-04-03

    申请人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    发明人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

    摘要翻译： 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。

    Process of making a dram cell arrangement
    8.
    发明授权
    Process of making a dram cell arrangement 失效
    制作电视剧排列的过程

    公开(公告)号：US5817552A

    公开(公告)日：1998-10-06

    申请号：US635526

    申请日：1996-04-22

    申请人： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofman ,  Wolfgang Krautschneider

    发明人： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofman ,  Wolfgang Krautschneider

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10876 ,  H01L27/10823

    摘要： For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of which is connected to a buried bit line. The DRAM cell arrangement can be produced with a storage-cell area of 4F.sup.2 by using only two masks, F being the minimum producible structure size in the respective technology.

    摘要翻译： 对于每个存储单元，DRAM单元布置具有垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储器节点，其存储电容器的沟道区域被栅电极环形地包围，并且第二源极 漏极区连接到埋地位线。 可以通过仅使用两个掩模来制造具有4F2的存储单元面积的DRAM单元布置，F是相应技术中的最小可生产结构尺寸。

    Integrated circuit including a vertical transistor and method
    9.
    发明授权
    Integrated circuit including a vertical transistor and method 有权
    集成电路包括垂直晶体管和方法

    公开(公告)号：US07838925B2

    公开(公告)日：2010-11-23

    申请号：US12173524

    申请日：2008-07-15

    申请人： Wolfgang Roesner ,  Franz Hofmann

    发明人： Wolfgang Roesner ,  Franz Hofmann

    IPC分类号： H01L29/732

    CPC分类号： H01L29/7827 ,  H01L21/2255 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/66734 ,  H01L29/7813

    摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.

    摘要翻译： 一种包括垂直晶体管和制造方法的集成电路。 在一个实施例中，垂直晶体管形成在半导体衬底的柱中。 埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。 第二绝缘层布置在接触结构的上方并与之相邻。 第一和第二绝缘层中的至少一个包括掺杂剂。 掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。 掺杂区域的掺杂浓度高于衬底掺杂剂浓度。