公开(公告)号：US20210336622A1

公开(公告)日：2021-10-28

申请号：US16857090

申请日：2020-04-23

Applicant: XILINX, INC.

Inventor： Steven P. YOUNG ,  Brian C. GAIDE

IPC: H03K19/17748 ,  G06F1/10 ,  G06F8/40 ,  H03K19/17736

Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

公开(公告)号：US20210143127A1

公开(公告)日：2021-05-13

申请号：US16679063

申请日：2019-11-08

Applicant: XILINX, INC.

Inventor： Praful JAIN ,  Steven P. YOUNG ,  Martin L. VOOGEL ,  Brian C. GAIDE

IPC: H01L25/065 ,  H01L25/00

Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.

公开(公告)号：US20240429145A1

公开(公告)日：2024-12-26

申请号：US18214381

申请日：2023-06-26

Applicant: XILINX, INC.

Inventor： Praful JAIN ,  Brian C. GAIDE ,  Martin L. VOOGEL

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe techniques to build multi-die field-programmable gate arrays (FPGAs) using chip-on-wafer (CoW) technology. In an embodiment, FPGA chiplets (i.e., dies) and an interposer substrate include respective hybrid bonding connectors. Metal layers of the interposer substrate are patterned to provide inter-die communications amongst the multiple dies via the hybrid bonding connectors, and the dies communicate with one another via the hybrid bonding connectors using a non-serialized protocol native to the FPGA. The dies may communicate with one another through edge-based hybrid bonding connectors (e.g., in a symmetrical fashion). The metal layers of the interposer substrate may also support intra-die communications (e.g., data, clocks, and/or controls) and/or provide power, clock(s), and/or configuration parameters to the dies via hybrid bonding connectors within central regions of the dies. The IC device may include more than 1000 tracks per millimeter (e.g., more than 1600, 2800, 3500, or greater).

公开(公告)号：US20220368330A1

公开(公告)日：2022-11-17

申请号：US17876456

申请日：2022-07-28

Applicant: XILINX, INC.

Inventor： Steven P. YOUNG ,  Brian C. GAIDE

IPC: H03K19/17748 ,  G06F1/10 ,  G06F8/40 ,  H03K19/17736

Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

公开(公告)号：US20220197329A1

公开(公告)日：2022-06-23

申请号：US17127525

申请日：2020-12-18

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE

IPC: G06F1/10 ,  H01L23/00

Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.

公开(公告)号：US20200303311A1

公开(公告)日：2020-09-24

申请号：US16571788

申请日：2019-09-16

Applicant: XILINX, INC.

Inventor： Steven P. YOUNG ,  Brian C. GAIDE

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/66

Abstract: Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.

公开(公告)号：US20240313781A1

公开(公告)日：2024-09-19

申请号：US18123160

申请日：2023-03-17

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Sagheer AHMAD ,  Trevor J. BAUER ,  Kenneth MA ,  David P. SCHULTZ ,  John O'DWYER ,  Richard W. SWANSON ,  Bhuvanachandran K. NAIR ,  Millind MITTAL

IPC: H03K19/17736 ,  G01R31/317 ,  H03K19/0175 ,  H03K19/17796

CPC classification number: H03K19/17744 ,  G01R31/31701 ,  H03K19/017581 ,  H03K19/17796

Abstract: Embodiments herein describe connecting an ASIC to another integrated circuit (or die) using inter-die connections. In one embodiment, an ASIC includes a fabric sliver (e.g., a small region of programmable logic circuitry). Inter-die fabric extension connections are used to connect the fabric sliver in the ASIC to fabric (e.g., programmable logic) in the other integrated circuit. These connections effectively extend the fabric in the ASIC to include the fabric in the other integrated circuit. Hardened IP blocks in the ASIC can then use the fabric sliver and the inter-die extension connections to access computer resources in the other integrated circuit.

公开(公告)号：US20240203968A1

公开(公告)日：2024-06-20

申请号：US18081461

申请日：2022-12-14

Applicant: XILINX, INC.

Inventor： Jaspreet Singh GANDHI ,  Brian C. GAIDE

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/5381 ,  H01L24/08 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/08155 ,  H01L2224/16225 ,  H01L2224/81

Abstract: A chip package and method for fabricating the same are provided that include hybrid bonded bridge dies connecting IC dies on adjacent die stacks. In one example, a chip package includes an interconnect routing structure, a first die stack and a second die stack. The first die stack includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The second die stack also includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The first bridge die is electrically and mechanically coupled to the top dies of the first and second die stacks. The first bridge die having solid state circuitry that connects circuitries of the top dies of the first and second die stacks.

公开(公告)号：US20240194645A1

公开(公告)日：2024-06-13

申请号：US18079631

申请日：2022-12-12

Applicant: XILINX, INC.

Inventor： Jay T. YOUNG ,  Davis Boyd MOORE ,  Sundeep Ram Gopal AGARWAL ,  Brian C. GAIDE

IPC: H01L25/065 ,  G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L25/0657 ,  G11C5/025 ,  G11C5/063 ,  H01L23/481 ,  H01L27/0207 ,  H01L27/0688 ,  H01L2225/06506

Abstract: An integrated circuit (IC) device includes a block of integrated circuitry that includes functional circuitry and configurable interface circuitry. The configurable interface circuitry includes output circuitry that routes a node of the functional circuitry to an output node of the block, and input circuitry that selectively routes the output node of the block or an input node of the block to the functional circuitry. The output circuitry may route a selectable subset of multiple nodes of the functional circuitry to respective output nodes of the block, and the input circuitry may be configured to route the output nodes of the block back to the functional circuitry in the absence of an adjacent block (e.g., to repurpose the output circuitry), or in addition to interfacing with the adjacent block.

公开(公告)号：US20210134760A1

公开(公告)日：2021-05-06

申请号：US16672077

申请日：2019-11-01

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Steven P. YOUNG

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78

Abstract: Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.