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    Die singulation and stacked device structures
    3.
    发明授权
    Die singulation and stacked device structures 有权

    公开(公告)号：US11075117B2

    公开(公告)日：2021-07-27

    申请号：US15904764

    申请日：2018-02-26

    Applicant: Xilinx, Inc.

    Inventor： Ganesh Hariharan ,  Raghunandan Chaware ,  Inderjit Singh

    IPC: H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/263 ,  H01L21/683 ,  H01L21/3065 ,  H01L23/00 ,  H01L23/31

    Abstract: Techniques for singulating dies from a respective workpiece and for incorporating one or more singulated die into a stacked device structure are described herein. In some examples, singulating a die from a workpiece includes chemically etching the workpiece in a scribe line. In some examples, singulating a die from a workpiece includes mechanically dicing the workpiece in a scribe line and forming a liner along a sidewall of the die. The die can be incorporated into a stacked device structure. The die can be attached to a substrate along with another die that is attached to the substrate. An encapsulant can be between each die and the substrate and laterally between the dies.

    Stacked silicon package assembly having enhanced lid adhesion
    6.
    发明授权
    Stacked silicon package assembly having enhanced lid adhesion 有权
    堆叠硅封装组件具有增强的盖子附着力

    公开(公告)号：US09418909B1

    公开(公告)日：2016-08-16

    申请号：US14820147

    申请日：2015-08-06

    Applicant: Xilinx, Inc.

    Inventor： Raghunandan Chaware ,  Inderjit Singh

    IPC: H01L23/10 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31

    CPC classification number: H01L23/10 ,  H01L23/053 ,  H01L23/3142 ,  H01L23/562 ,  H01L24/26 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/8385 ,  H01L2924/16196

    Abstract: A method and apparatus are provided which improve the adhesion of a lid to an IC die of an IC (chip) package. In one embodiment, a chip package assembly is provided that includes an IC die, a package substrate and a lid. The IC die is coupled to the package substrate. The lid has a first surface and a second surface. The second surface of the lid faces away from the first surface and towards the IC die. The second surface of the lid has a plurality of engineered features. The adhesive couples the plurality of engineered features of the lid to the IC die.

    Abstract translation: 提供了一种提高盖子与IC（芯片）封装的IC芯片的密合性的方法和装置。 在一个实施例中，提供了包括IC管芯，封装基板和盖子的芯片封装组件。 IC管芯耦合到封装衬底。 盖具有第一表面和第二表面。 盖的第二表面背离第一表面并朝向IC芯片。 盖的第二表面具有多个工程特征。 粘合剂将盖的多个工程特征耦合到IC管芯。

    DIE SINGULATION AND STACKED DEVICE STRUCTURES
    7.
    发明申请
    DIE SINGULATION AND STACKED DEVICE STRUCTURES 审中-公开

    公开(公告)号：US20190267287A1

    公开(公告)日：2019-08-29

    申请号：US15904764

    申请日：2018-02-26

    Applicant: Xilinx, Inc.

    Inventor： Ganesh Hariharan ,  Raghunandan Chaware ,  Inderjit Singh

    IPC: H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

    Abstract: Techniques for singulating dies from a respective workpiece and for incorporating one or more singulated die into a stacked device structure are described herein. In some examples, singulating a die from a workpiece includes chemically etching the workpiece in a scribe line. In some examples, singulating a die from a workpiece includes mechanically dicing the workpiece in a scribe line and forming a liner along a sidewall of the die. The die can be incorporated into a stacked device structure. The die can be attached to a substrate along with another die that is attached to the substrate. An encapsulant can be between each die and the substrate and laterally between the dies.

    Multi-die wafer-level test and assembly without comprehensive individual die singulation
    8.
    发明授权
    Multi-die wafer-level test and assembly without comprehensive individual die singulation 有权

    公开(公告)号：US10032682B1

    公开(公告)日：2018-07-24

    申请号：US15359280

    申请日：2016-11-22

    Applicant: Xilinx, Inc.

    Inventor： Matthew H. Klein ,  Raghunandan Chaware ,  Glenn O'Rourke

    IPC: H01L21/66 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00

    Abstract: Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.

    Integrated circuit package testing
    10.
    发明授权
    Integrated circuit package testing 有权
    集成电路封装测试

    公开(公告)号：US09341668B1

    公开(公告)日：2016-05-17

    申请号：US14242760

    申请日：2014-04-01

    Applicant: Xilinx, Inc.

    Inventor： Ganesh Hariharan ,  Raghunandan Chaware ,  Glenn O'Rourke ,  Inderjit Singh ,  Eric J. Thorne ,  David E. Schweigler

    IPC: G01R31/00 ,  G01R31/26 ,  G01R1/04

    CPC classification number: G01R31/2889 ,  G01R1/0416

    Abstract: A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.

    Abstract translation: 可测试电路装置包括集成电路（IC）封装。 IC封装包括封装衬底，直接安装在具有级别1互连的封装衬底上的插入件以及直接安装在具有0级互连的插入器上的至少一个IC管芯。 IC封装的封装基板直接安装在具有2级互连的焊接球栅格阵列的连接器板上。 0级，1级和2级互连包括各自的功率，配置和测试互连。 连接器板的电源，配置和测试端子耦合到2级互连的电源，配置和测试互连。

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