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    Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating
    1.
    发明授权
    Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating 有权
    具有易失性和多位，非易失性功能和操作方法的半导体存储器

    公开(公告)号：US08923052B2

    公开(公告)日：2014-12-30

    申请号：US13196471

    申请日：2011-08-02

    申请人： Yuniarto Widjaja

    发明人： Yuniarto Widjaja

    IPC分类号： G11C11/34 ,  G11C14/00 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  H01L27/115 ,  G11C16/04

    CPC分类号： G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

    摘要： A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, and a control gate positioned above the trapping layer.

    摘要翻译： 描述了半导体存储单元，包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在衬底的第二位置处嵌入在衬底中并具有第二导电类型，使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间，并且用作浮体 将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 包括第一和第二存储位置的捕获层被配置为将数据彼此独立地存储为非易失性存储器，以及位于捕获层上方的控制栅极。

    Semiconductor memory having electrically floating body transistor
    5.
    发明授权
    Semiconductor memory having electrically floating body transistor 有权
    具有电浮体晶体管的半导体存储器

    公开(公告)号：US08174886B2

    公开(公告)日：2012-05-08

    申请号：US13244839

    申请日：2011-09-26

    申请人： Yuniarto Widjaja ,  Zvi Or-Bach

    发明人： Yuniarto Widjaja ,  Zvi Or-Bach

    IPC分类号： G01C14/00

    CPC分类号： G11C11/404 ,  G11C11/56 ,  G11C11/565 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881

    摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

    摘要翻译： 半导体存储单元包括被配置为被充电到指示存储单元的状态的电平的浮动体区域; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 位于所述第一和第二区域之间的门; 以及背偏置区域，被配置为将电荷注入或从所述浮体区域中提取电荷以维持存储单元的所述状态。 将背偏置施加到背偏置区域将电荷泄漏偏离浮体，并对电池执行保持操作。 单元可以是多级单元。 公开了用于制造存储器件的存储器单元阵列。

    SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING
    7.
    发明申请
    SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING 有权
    具有两种挥发性和非挥发性功能的半导体存储器及其操作方法

    公开(公告)号：US20110042736A1

    公开(公告)日：2011-02-24

    申请号：US12915831

    申请日：2010-10-29

    申请人： Yuniarto Widjaja

    发明人： Yuniarto Widjaja

    IPC分类号： H01L29/788 ,  H01L29/792

    CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

    摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory, first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.

    摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括从衬底延伸的翅片结构，鳍结构包括具有第一导电类型的浮动衬底区域，配置为将数据存储为易失性存储器，与浮置衬底区域接口的第一和第二区域，第一和第 具有第二导电类型的第二区域; 位于浮置衬底区域的相对侧的第一和第二浮栅或俘获层; 位于所述浮置衬底区域和所述浮置栅极或俘获层之间的第一绝缘层，所述浮置栅极或俘获层被配置为接收由所述易失性存储器存储的数据的传送，并将所述数据作为非易失性存储器存储在所述浮置栅极或俘获层中 在中断存储器单元的电源时; 围绕浮动栅极或捕获层和浮置衬底区域的控制栅极; 以及位于所述浮置栅极或俘获层之间的第二绝缘层和所述控制栅极; 所述衬底包括将所述浮置衬底区域与所述隔离层下方的所述衬底的一部分隔离的隔离层。

    MEMORY CELLS, MEMORY CELL ARRAYS, METHODS OF USING AND METHODS OF MAKING
    9.
    发明申请
    MEMORY CELLS, MEMORY CELL ARRAYS, METHODS OF USING AND METHODS OF MAKING 有权
    记忆细胞，记忆细胞阵列，使用方法和制备方法

    公开(公告)号：US20090316492A1

    公开(公告)日：2009-12-24

    申请号：US12552903

    申请日：2009-09-02

    申请人： Yuniarto Widjaja

    发明人： Yuniarto Widjaja

    IPC分类号： G11C7/00 ,  H01L29/78 ,  H01L45/00 ,  H01L27/06 ,  H01L21/336 ,  G11C5/14

    CPC分类号： G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/1023 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H01L45/06 ,  H01L45/144 ,  H01L45/145

    摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

    摘要翻译： 提供半导体存储单元和存储单元阵列在至少一个实施例中，存储单元包括具有顶表面的衬底，该衬底具有选自p型导电类型和n型导电类型的第一导电类型 ; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型，所述第一区域形成在所述基板中并暴露在所述顶表面处; 具有第二导电类型的第二区域，第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区，所述体区具有第一导电类型; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

    Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
    10.
    发明授权
    Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
    双向分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法

    公开(公告)号：US07544569B2

    公开(公告)日：2009-06-09

    申请号：US11516431

    申请日：2006-09-05

    申请人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

    发明人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42336 ,  G11C16/0425 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328

    摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

    摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。 多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。 多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。 每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。 多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。 每个选择门位于一对浮动门之间。