公开(公告)号：US08836373B2

公开(公告)日：2014-09-16

申请号：US14093356

申请日：2013-11-29

申请人： SK hynix Inc.

发明人： Dong-Suk Shin

IPC分类号： G01R25/00 ,  H03L7/089

CPC分类号： H03L7/089 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/0028

摘要： A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

公开(公告)号：US07629856B2

公开(公告)日：2009-12-08

申请号：US11588877

申请日：2006-10-27

申请人： Edwin Thaller

发明人： Edwin Thaller

IPC分类号： H03K3/03

CPC分类号： H03K5/133 ,  H03F3/45237 ,  H03F3/45475 ,  H03F2203/45138 ,  H03F2203/45236 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45366 ,  H03F2203/45652 ,  H03K3/0315 ,  H03K3/356113 ,  H03K2005/00071 ,  H03K2005/00208 ,  H03K2005/00215 ,  H03K2005/00228 ,  H03K2005/0028 ,  H03L7/0995

摘要： A delay stage for a semiconductor device includes at least one delay branch and at least one controllable switching apparatus. The at least one controllable switching apparatus is configured to connect a predefined amount of the at least one delay branch to a supply voltage.

摘要翻译： 半导体器件的延迟级包括至少一个延迟分支和至少一个可控开关装置。 至少一个可控开关装置被配置为将预定量的至少一个延迟支路连接到电源电压。

公开(公告)号：US5130564A

公开(公告)日：1992-07-14

申请号：US620720

申请日：1990-12-03

申请人： Yun-Seung Sin

发明人： Yun-Seung Sin

IPC分类号： G11C11/4076 ,  H03K4/02 ,  H03K5/00 ,  H03K5/13 ,  H03K19/003

CPC分类号： H03K5/133 ,  H03K2005/00071 ,  H03K2005/0028

摘要： A signal delay circuit includes a driving circuit for driving an output signal with a voltage swing voltage between a supply voltage and a ground voltage. The signal delay circuit further includes a varactor load which is coupled to the output signal and has a capacitance which increases according to the supply voltage within a variation range of the supply voltage. The varactor load keeps the delay characteristic of the signal propagation circuit independent of the change of the supply voltage, thereby ensuring high speed operation and improved reliability of the CMOS semiconductor integrated circuit.

摘要翻译： 信号延迟电路包括用于以电源电压和接地电压之间的电压摆幅电压驱动输出信号的驱动电路。 信号延迟电路还包括可变电抗器负载，其耦合到输出信号并且具有根据电源电压的变化范围内的电源电压而增加的电容。 变容二极管负载保持信号传播电路的延迟特性，与电源电压的变化无关，从而确保CMOS半导体集成电路的高速运行和可靠性。

公开(公告)号：US20180302070A1

公开(公告)日：2018-10-18

申请号：US15489221

申请日：2017-04-17

申请人： Ciena Corporation

发明人： Mahdi Parvizi ,  Sadok Aouini ,  Naim Ben-Hamida

IPC分类号： H03K5/13

CPC分类号： H03K5/13 ,  H03K5/134 ,  H03K2005/00019 ,  H03K2005/00195 ,  H03K2005/0028

摘要： A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.

公开(公告)号：US20140103987A1

公开(公告)日：2014-04-17

申请号：US14093364

申请日：2013-11-29

申请人： SK hynix Inc.

发明人： Dong-Suk SHIN

IPC分类号： H03K5/14

CPC分类号： H03L7/089 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/0028

摘要： A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

摘要翻译： 一种相位差量化电路的延迟值控制电路，其中相位差量化电路具有二进制权重的第一至第N（N是等于或大于2的整数）延迟单元。 延迟值控制电路包括复制Ath（2＆amp; NlE; A＆N; E; N）延迟单元的复制延迟单元; 以及延迟控制单元，被配置为比较从延迟输入信号产生的第一输出信号与第一延迟单元的相位和从延迟输入信号而产生的第二输出信号的相位与Ath延迟单元和副本 延迟单元，并且被配置为使用比较结果来控制Ath延迟单元的延迟值。

公开(公告)号：US4939677A

公开(公告)日：1990-07-03

申请号：US150401

申请日：1988-01-15

申请人： Taiichi Otuji ,  Naoaki Narumi

发明人： Taiichi Otuji ,  Naoaki Narumi

IPC分类号： G01R31/319 ,  H03K5/00 ,  H03K5/13 ,  H03K5/15 ,  H04L7/02

CPC分类号： H03K5/13 ,  G01R31/31922 ,  H03K5/131 ,  H03K5/133 ,  H03K5/15 ,  H03K2005/00045 ,  H03K2005/00267 ,  H03K2005/0028

摘要： Timing-signal delay equipment which provides an adjustable delay time, equal to a multiple of a predetermined time unit, to an input signal pulse is used as a timing source required in a circuit tester of LSIs (semiconductor large-scale integrated circuits). The timing-signal delay equipment has a plurality of delay elements (D.sub.ij 's) with weighted delay times arranged in a matrix form; a selector (S) coupled with the matrix for selecting one of the delay elements for each column of the matrix, wherein the selected delay elements are connected in series; and an arithmetic control circuit (M) that controls the selectors based on a set-up value of delay time and an error in delay time of each delay equipment. In order to provide a delay time which is equal to a multiple of a predetermined time unit in spite of an error in delay time of each delay element, either a correction matrix is connected in series to the matrix or the weight of each delay element is modified.

摘要翻译： PCT No.PCT / JP87 / 00734 Sec。 371日期1988年1月15日 102（e）日期1988年1月15日PCT提交1987年10月2日PCT公布。 出版物WO88 / 02577 日期：1988年7月4日。将用于向输入信号脉冲提供等于预定时间单位的可调节延迟时间的定时信号延迟设备用作LSI的电路测试仪（半导体大型 标准集成电路）。 定时信号延迟设备具有以矩阵形式布置的加权延迟时间的多个延迟元件（Dij's）; 与所述矩阵耦合的选择器（S），用于选择所述矩阵的每列的所述延迟元件中的一个，其中所选择的延迟元件串联连接; 以及算术控制电路（M），其基于延迟时间的设置值和每个延迟设备的延迟时间的误差来控制选择器。 为了提供等于预定时间单位的倍数的延迟时间，尽管每个延迟元件的延迟时间有误差，校正矩阵与矩阵串联连接，或者每个延迟元件的权重是 改性。

公开(公告)号：US20180307262A1

公开(公告)日：2018-10-25

申请号：US15497051

申请日：2017-04-25

申请人： Honeywell International Inc.

发明人： Xiaoxin Feng ,  Weston Roper

IPC分类号： G05F3/24 ,  H03K17/082 ,  H03K19/003 ,  G05F3/26 ,  G05F1/10

CPC分类号： G05F3/242 ,  G05F1/10 ,  G05F3/26 ,  H03K17/0822 ,  H03K19/00384 ,  H03K2005/0028

摘要： The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.

公开(公告)号：US20140368249A1

公开(公告)日：2014-12-18

申请号：US14026698

申请日：2013-09-13

申请人： SK hynix Inc.

发明人： Kwang Su LEE

IPC分类号： H03K3/011

CPC分类号： H03K5/131 ,  H03K2005/00247 ,  H03K2005/0028

摘要： The present invention relates to a delay control circuit and technology in which the amount of delay can be regularly maintained although Process, Voltage, and Temperature (PVT) conditions are changed. The delay control circuit of the present invention includes a ZQ calibration unit configured to generate an impedance code into which a change of PVT conditions has been incorporated, a voltage trimming unit configured to control a level of a trimming voltage at a calibration node, and a delay compensation unit configured to compensate for the amount of delay by controlling an effective capacitance value of a capacitor.

摘要翻译： 本发明涉及一种延迟控制电路和技术，其中虽然改变了过程，电压和温度（PVT）条件，但是可以定期地维持延迟量。 本发明的延迟控制电路包括：ZQ校准单元，被配置为产生已经并入PVT条件的变化的阻抗代码;被配置为控制校准节点处的微调电压的电平的电压修整单元，以及 延迟补偿单元，被配置为通过控制电容器的有效电容值来补偿延迟量。

公开(公告)号：US07619457B1

公开(公告)日：2009-11-17

申请号：US11607641

申请日：2006-12-01

申请人： Rifeng Mai

发明人： Rifeng Mai

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  H03K5/133 ,  H03K2005/00136 ,  H03K2005/0028

摘要： A delay circuit is described having a variable capacitor and a triggering circuit. The variable capacitor and the triggering circuit may both comprise transistors. With both the variable capacitor and the triggering circuit dependent on the threshold voltage, the delay circuit may be less sensitive to process variations. The delay circuit may also include a capacitor, a first triggering circuit, a second triggering circuit, and a pull down circuit. The capacitor may discharge at a first rate, triggering the first triggering circuit which, in turn, activates the pull down circuit to pull down the capacitor at a second rate that is faster than the first rate. The second triggering circuit is triggered as the capacitor is pulled down, thereby reducing the effect of input signal noise on the output of the delay circuit. The discharging of the capacitor may be adjusted by a control input thereby making the delay of the delay circuit programmable.

摘要翻译： 描述了具有可变电容器和触发电路的延迟电路。 可变电容器和触发电路都可以包括晶体管。 随着可变电容器和触发电路两者都取决于阈值电压，延迟电路可能对工艺变化不那么敏感。 延迟电路还可以包括电容器，第一触发电路，第二触发电路和下拉电路。 电容器可以以第一速率放电，触发第一触发电路，其又激活下拉电路，以比第一速率快的第二速率下拉电容器。 当电容器被拉下时，触发第二触发电路，从而减少输入信号噪声对延迟电路输出的影响。 可以通过控制输入调节电容器的放电，从而使延迟电路的延迟可编程。

公开(公告)号：US3909637A

公开(公告)日：1975-09-30

申请号：US52590374

申请日：1974-11-21

申请人： IBM

发明人： DORLER JACK A

IPC分类号： H03K5/04 ,  H01L21/822 ,  H01L27/04 ,  H03K5/00 ,  H03K5/12 ,  H03K6/00 ,  H03K6/04 ,  H03K17/28 ,  H03K19/086 ,  H03K3/26 ,  H01L29/92

CPC分类号： H03K5/12 ,  H03K6/04 ,  H03K2005/00045 ,  H03K2005/00163 ,  H03K2005/0028

摘要： A method and apparatus for increasing the delays in transitions at controlled terminals in a non-linear integrated circuit by increasing the effective capacitance at the controlled terminals. This can be accomplished by capacitively cross-coupling at opposing phase controlled terminals. The capacitive crosscoupling is effected by connecting two P/N junction diodes in series with opposite directions of conductivity such that the capacitances across the junctions of the diodes are effectively connected in series.

摘要翻译： 一种用于通过增加受控终端的有效电容来增加非线性集成电路中受控终端的转变延迟的方法和装置。 这可以通过在相对相位控制端子处的电容交叉耦合来实现。 电容交叉耦合通过将两个P / N结二极管串联连接到相反的导电方向来实现，使得跨过二极管的结的电容被有效地串联连接。