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    Plated terminations
    91.
    发明申请
    Plated terminations 有权

    公开(公告)号：US20040090732A1

    公开(公告)日：2004-05-13

    申请号：US10632514

    申请日：2003-08-01

    Applicant: AVX Corporation

    Inventor： Andrew P. Ritter ,  Robert Heistand II ,  John L. Galvagni ,  Sriram Dattaguru

    IPC: H01G004/228

    CPC classification number: H01C1/14 ,  C23C18/1605 ,  C23C18/1639 ,  C23C18/1886 ,  H01C7/008 ,  H01C7/10 ,  H01G4/005 ,  H01G4/232 ,  H01G4/30 ,  H05K1/181 ,  Y02P70/611 ,  Y10T29/43 ,  Y10T29/435

    Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on one or both of top and bottom surfaces of a monolithic structure can facilitate the formation of selective wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

    Discrete component array
    92.
    发明申请
    Discrete component array 有权
    离散元件阵列

    公开(公告)号：US20030231477A1

    公开(公告)日：2003-12-18

    申请号：US10409024

    申请日：2003-04-08

    Applicant: AVX Corporation

    Inventor： William F. Vierow ,  Dehart G. Scrantom III ,  Walter Koda ,  Victor Martinez

    IPC: H05K007/14 ,  H05K007/18

    CPC classification number: H01G4/38

    Abstract: Integrated passive component assemblies utilize array shell or array frame receiving structures to isolate and protect discrete passive components and provide a modular configuration for mounting to a substrate. Receiving structure embodiments include a base portion, spacer ribs, and optional side walls. Spacer ribs may be connected or provided in opposing spacer rib portions to effectively isolate adjacent component terminations. Standoff features may be incorporated into select embodiments of the disclosed technology to aid in device mounting and to facilitate post-affixment cleaning and visual termination contact. Discrete passive components in accordance with the present subject matter may include select combinations of resistors, capacitors, inductors, and other suitable devices.

    Abstract translation: 集成的无源元件组件利用阵列外壳或阵列框架接收结构来隔离和保护分立的无源元件，并提供用于安装到基板的模块化配置。 接收结构实施例包括基部，间隔肋和可选的侧壁。 间隔肋可以连接或设置在相对的间隔肋部分中以有效地隔离相邻的部件终端。 间隔特征可以被结合到所公开技术的选择实施例中，以帮助装置安装并且便于后固定清洁和视觉终止接触。 根据本主题的分立无源部件可以包括电阻器，电容器，电感器和其它合适的器件的选择组合。

    Cascade capacitor
    93.
    发明申请
    Cascade capacitor 失效
    级联电容

    公开(公告)号：US20030072125A1

    公开(公告)日：2003-04-17

    申请号：US10234972

    申请日：2002-09-04

    Applicant: AVX Corporation

    Inventor： John L. Galvagni ,  Robert Heistand II ,  Georghe Korony

    IPC: H01G004/228

    CPC classification number: H01G4/228 ,  H01G2/00 ,  H01G4/30 ,  H01G4/385 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49082 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: Multi-layer and cascade capacitors for use in high frequency applications and other environments are disclosed. The subject capacitor may comprise multiple capacitor components or aspects thereof in an integrated package. Such components may include, for example, thin film BGA components, interdigitated capacitor (IDC) configurations, double-layer electrochemical capacitors, surface mount tantalum products, multilayer capacitors, single layer capacitors, and others. Exemplary embodiments of the present subject matter preferably encompass at least certain aspects of thin film BGA techniques and/or IDC-style configurations. Features for attachment and interconnection are provided that facilitate low ESL while maintaining a given capacitance value. Additional advantages include low ESR and decoupling performance over a broad band of operational frequencies. More particularly, the presently disclosed technology provides for exemplary capacitors that may function over a frequency range from kilohertz up to several gigahertz, and that may also be characterized by a wide range of capacitance values. An additionally disclosed feature of the present subject matter is to incorporate dielectric layers of varied thicknesses to broaden the resonancy curve associated with a particular configuration.

    Abstract translation: 公开了用于高频应用和其他环境的多层和级联电容器。 本发明电容器可以包括多个电容器组件或其集成封装中的方面。 这样的部件可以包括例如薄膜BGA部件，叉指电容器（IDC）配置，双层电化学电容器，表面贴装钽产品，多层电容器，单层电容器等。 本主题的示例性实施例优选地包括薄膜BGA技术和/或IDC式配置的至少某些方面。 提供用于附接和互连的特征，其在保持给定的电容值的同时促进低ESL。 另外的优点包括在宽频带工作频率下的低ESR和去耦性能。 更具体地，本公开的技术提供了可以在从千赫兹到几千兆赫兹的频率范围内起作用的示例性电容器，并且还可以通过宽范围的电容值来表征。 本主题的另外公开的特征是结合不同厚度的电介质层以扩大与特定配置相关联的共振曲线。

    Solderless wire-to-board single pair ethernet connection system
    95.
    发明授权
    Solderless wire-to-board single pair ethernet connection system 有权

    公开(公告)号：US11929568B2

    公开(公告)日：2024-03-12

    申请号：US17483348

    申请日：2021-09-23

    Applicant: AVX Corporation

    Inventor： Jackie Mincey

    IPC: H01R12/75 ,  H01R4/2433 ,  H01R12/58 ,  H01R12/70 ,  H01R13/627 ,  H01R13/6582 ,  H01R12/57

    CPC classification number: H01R12/75 ,  H01R4/2433 ,  H01R12/58 ,  H01R12/7023 ,  H01R13/6275 ,  H01R13/6582 ,  H01R12/57

    Abstract: This disclosure provides a method and apparatus for a single pair Ethernet (SPE) wire-to-board connector. The SPE connector may include a female connector portion and a male connector portion. The female connector portion may include a first electrical contact having a first press-fit pin and a first female portion, a second electrical contact having a second press-fit pin and a second female portion, and a first outer shield, the first outer shield mechanically secured to the first insulative housing. The first and second electrical contacts may be positioned partially within the first insulative housing. The male connector portion includes a third electrical contact comprising a first insulation displacement contact (IDC) portion and a first male portion, a fourth electrical contact comprising a second DC portion and a second male portion, and a second outer shield, the second outer shield mechanically secured to a second insulative housing.

    Multilayer capacitor having open mode electrode configuration and flexible terminations
    100.
    发明授权
    Multilayer capacitor having open mode electrode configuration and flexible terminations 有权

    公开(公告)号：US11664165B2

    公开(公告)日：2023-05-30

    申请号：US16850132

    申请日：2020-04-16

    Applicant: AVX Corporation

    Inventor： Frank Hodgkinson ,  Elaine Boyle

    IPC: H01G4/248 ,  H01G4/12 ,  H01G4/012 ,  H01G4/30

    CPC classification number: H01G4/248 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30

    Abstract: A multilayer ceramic capacitor may include a monolithic body and interleaved first and second pluralities of electrodes extending from the first and second ends, respectively, of the monolithic body towards opposite ends of the monolithic body. A first margin distance and a second margin distance may be formed, respectively, between the electrodes and the opposite ends of the monolithic body. First and second external terminations may be respectively disposed along the first end and second end of the monolithic body and respectively connected with the first and second plurality of electrodes. A margin ratio between a length of the monolithic body and the first margin distance and/or second margin distance may be less than about 10. At least one of the first external termination or the second external termination may include a conductive polymeric composition.

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