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91.发明申请APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE 有权用于改善量子阱器件中并联导通的装置和方法公开(公告)号：US20120326123A1
公开(公告)日：2012-12-27
申请号：US13545358
申请日：2012-07-10
IPC分类号： H01L29/02
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。 可以描述和要求保护其他实施例。
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公开(公告)号：US20120309173A1
公开(公告)日：2012-12-06
申请号：US13563456
申请日：2012-07-31
申请人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
发明人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译： 本公开涉及制造微电子器件的领域。 在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。
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公开(公告)号：US08168508B2
公开(公告)日：2012-05-01
申请号：US12346554
申请日：2008-12-30
申请人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
发明人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L21/76
CPC分类号： H01L29/06 , B82Y99/00 , H01L21/76205 , H01L21/76224 , H01L29/0657 , H01L29/66795 , H01L29/775 , H01L29/7854
摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
摘要翻译： 提供一种方法。 该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。
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公开(公告)号：US20110147697A1
公开(公告)日：2011-06-23
申请号：US12653847
申请日：2009-12-18
申请人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
发明人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译： 本公开涉及制造微电子器件的领域。 在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。
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公开(公告)号：US07777282B2
公开(公告)日：2010-08-17
申请号：US12228457
申请日：2008-08-13
CPC分类号： H01L21/26586 , H01L21/2652 , H01L29/66545 , H01L29/7835
摘要： A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.
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96.发明申请Self-aligned tunneling pocket in field-effect transistors and processes to form same 有权在场效应晶体管中的自对准隧道口和形成相同的工艺公开(公告)号：US20100038713A1
公开(公告)日：2010-02-18
申请号：US12228457
申请日：2008-08-13
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/2652 , H01L29/66545 , H01L29/7835
摘要： A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.
摘要翻译： 微电子器件包括位于不对称半导体内的隧道槽，其包括源阱和漏极井。 通过从栅极隔离物去除虚拟栅极电极并且将隧穿槽注入半导体本体或者作为半导体本体的一部分的外延膜中，通过自对准工艺形成隧穿袋。
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公开(公告)号：US20200091274A1
公开(公告)日：2020-03-19
申请号：US16134876
申请日：2018-09-18
申请人： Abhishek SHARMA , Ravi PILLARISETTY , Brian DOYLE , Elijah KARPOV , Prashant MAJHI , Gilbert DEWEY , Benjamin CHU-KUNG , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI
发明人： Abhishek SHARMA , Ravi PILLARISETTY , Brian DOYLE , Elijah KARPOV , Prashant MAJHI , Gilbert DEWEY , Benjamin CHU-KUNG , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI
摘要： Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a gate dielectric layer adjacent to the channel layer, and a gate electrode separated from the channel layer by the gate dielectric layer. The gate dielectric layer includes a non-linear gate dielectric material. The gate electrode, the channel layer, and the gate dielectric layer form a non-linear capacitor. Other embodiments may be described and/or claimed.
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98.发明申请INTEGRATING VLSI-COMPATIBLE FIN STRUCTURES WITH SELECTIVE EPITAXIAL GROWTH AND FABRICATING DEVICES THEREON 有权集成具有选择性外延生长和制造设备的VLSI兼容FIN结构公开(公告)号：US20160204037A1
公开(公告)日：2016-07-14
申请号：US14777736
申请日：2013-06-28
申请人： Niti Goel , Ravi Pillarisetty , Willy Rachmady , Jack T. Kavalieros , Gilbert Dewey , Benjamin Chu-Kung , Marko Radosavljevic , Matthew V. Metz , Niloy Mukherjee , Robert S. Chau
发明人： Niti Goel , Ravi Pillarisetty , Willy Rachmady , Jack T. Kavalieros , Gilbert Dewey , Benjamin Chu-Kung , Marko Radosavljevic , Matthew V. Metz , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L21/8238 , H01L21/762 , H01L21/02
CPC分类号： H01L21/823807 , H01L21/0245 , H01L21/02455 , H01L21/02502 , H01L21/02532 , H01L21/02538 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L21/823431 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/1054 , H01L29/267 , H01L29/66795
摘要： Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.
摘要翻译： 通过从在浅沟槽隔离（STI）区域之间形成的第一沟槽的底部的衬底表面外延生长第一类型材料的第一外延区域，形成不同的n型和p型器件鳍。 STI区域和第一沟槽高度至少是其宽度的1.5倍。 蚀刻掉STI区域以暴露衬底的顶表面以在第一外延区域之间形成第二沟槽。 在第一外延区域的侧壁上的第二沟槽中形成间隔材料层。 在第二外延区域之间的第二沟槽的底部的衬底表面生长第二类型材料的第二外延区域。 可以从第一和第二外延区域形成正对和p型翅片对。 翅片是共同整合的，并且从材料界面晶格失配减少缺陷。
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公开(公告)号：US09245989B2
公开(公告)日：2016-01-26
申请号：US13976414
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L29/775 , H01L29/66 , G05F3/02 , H01L29/786 , B82Y10/00 , H01L29/06 , H01L29/20
CPC分类号： H01L29/0673 , B82Y10/00 , G05F3/02 , H01L21/02603 , H01L21/02636 , H01L21/225 , H01L21/283 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/32133 , H01L21/324 , H01L29/04 , H01L29/0676 , H01L29/068 , H01L29/2003 , H01L29/41725 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/66462 , H01L29/66469 , H01L29/775 , H01L29/78696
摘要： Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, and drain and source contacts similarly coaxially wrap completely around the drain and source regions.
摘要翻译： 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，并且漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。
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公开(公告)号：US09159823B2
公开(公告)日：2015-10-13
申请号：US13977188
申请日：2011-12-09
申请人： Van H. Le , Benjamin Chu-Kung , Harold Hal W. Kennel , Willy Rachmady , Ravi Pillarisetty , Jack T. Kavalieros
发明人： Van H. Le , Benjamin Chu-Kung , Harold Hal W. Kennel , Willy Rachmady , Ravi Pillarisetty , Jack T. Kavalieros
IPC分类号： H01L29/78 , H01L29/66 , H01L29/786 , H01L29/423 , H01L29/06
CPC分类号： H01L29/0673 , H01L21/02532 , H01L21/283 , H01L29/0649 , H01L29/0847 , H01L29/1054 , H01L29/155 , H01L29/161 , H01L29/165 , H01L29/42392 , H01L29/66431 , H01L29/66477 , H01L29/66651 , H01L29/66795 , H01L29/78 , H01L29/7842 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/78681 , H01L29/78687 , H01L29/78696
摘要： Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
摘要翻译： 提供具有包括压缩和拉伸应变外延材料的交替层的沟道区的晶体管结构。 交替的外延层可以在单和多晶体管结构中形成沟道区。 在替代实施例中，两个交替层中的一个被选择性地蚀刻掉以形成剩余材料的纳米带或纳米线。 得到的应变纳米带或纳米线形成晶体管结构的沟道区。 还提供了包括晶体管的计算设备，所述晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区，以及包括包含由应变纳米带或纳米线组成的沟道区的晶体管的计算器件。
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