公开(公告)号：US20130298088A1

公开(公告)日：2013-11-07

申请号：US13464116

申请日：2012-05-04

Applicant: Hsin-Chang Lee ,  Chia-Jen Chen ,  Yeh Lee-Chih ,  Sheng-Chi Chin ,  Ting-Hao Hsu ,  Anthony Yen

Inventor： Hsin-Chang Lee ,  Chia-Jen Chen ,  Yeh Lee-Chih ,  Sheng-Chi Chin ,  Ting-Hao Hsu ,  Anthony Yen

IPC: G06F17/50

CPC classification number: G03F1/84 ,  G03F1/72

Abstract: A method and system for measuring layer overlay and for inspecting a mask for defects unrelated to overlay utilizing a singe comprehensive tool is disclosed. An exemplary method includes receiving a mask design database that corresponds to a mask and has a die area with a mask database feature. A mask image of the mask is received, and a comprehensive inspection system compares the mask image to the mask design database in order to detect mask defects that are not related to layer alignment. The system produces mask defect information corresponding to the mask defects. The comprehensive inspection system also compares the mask image to the mask design database to determine a database-to-mask offset. From the database-to-mask offset, a mask overlay characteristic is determined.

Abstract translation: 公开了一种用于测量层叠覆盖层的方法和系统，并且用于使用单个综合工具来检查与覆盖无关的缺陷的掩模。 一种示例性方法包括接收对应于掩模并且具有掩模数据库特征的管芯区域的掩模设计数据库。 接收掩模的掩模图像，并且综合检查系统将掩模图像与掩模设计数据库进行比较，以便检测与层对齐无关的掩模缺陷。 系统产生对应于掩模缺陷的掩模缺陷信息。 综合检查系统还将掩模图像与掩模设计数据库进行比较，以确定数据库对掩模偏移量。 从数据库到掩码偏移，确定掩模覆盖特性。

公开(公告)号：US20130280643A1

公开(公告)日：2013-10-24

申请号：US13451705

申请日：2012-04-20

Applicant: Pei-Cheng Hsu ,  Chih-Tsung Shih ,  Chia-Jen Chen ,  Tsiao-Chen Wu ,  Shinn-Sheng Yu ,  Hsin-Chang Lee ,  Anthony Yen

Inventor： Pei-Cheng Hsu ,  Chih-Tsung Shih ,  Chia-Jen Chen ,  Tsiao-Chen Wu ,  Shinn-Sheng Yu ,  Hsin-Chang Lee ,  Anthony Yen

IPC: G03F1/24

CPC classification number: G03F1/24 ,  G03F1/48 ,  H01L21/0337

Abstract: A reflective mask is described. The mask includes a low thermal expansion material (LTEM) substrate, a conductive layer deposited on a first surface of the LTEM substrate, a stack of reflective multilayers (ML) deposited on a second surface of the LTEM substrate, a capping layer deposited on the stack of reflective ML, a first absorption layer deposited on the first capping layer, a main pattern, and a border ditch. The border ditch reaches to the capping layer, the second absorption layer deposited inside the border ditch, and the second absorption layer contacts the capping layer.

Abstract translation: 描述了一种反光罩。 掩模包括低热膨胀材料（LTEM）衬底，沉积在LTEM衬底的第一表面上的导电层，沉积在LTEM衬底的第二表面上的反射多层堆叠（ML），沉积在 堆叠的反射ML，沉积在第一盖层上的第一吸收层，主图案和边界沟。 边界沟到达覆盖层，第二吸收层沉积在边界沟内，第二吸收层接触封盖层。

公开(公告)号：US20130277759A1

公开(公告)日：2013-10-24

申请号：US13452516

申请日：2012-04-20

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681

Abstract: A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.

Abstract translation: 一种器件包括半导体衬底和彼此平行的多个半导体鳍片，其中多个半导体鳍片是半导体衬底的一部分。 浅沟槽隔离（STI）区域位于多个半导体鳍片的一侧。 STI区域具有顶表面和非平坦底表面，其中多个半导体鳍片在STI区域的顶表面之上。

公开(公告)号：US20130221448A1

公开(公告)日：2013-08-29

申请号：US13408538

申请日：2012-02-29

Applicant: Chia-Wei Chang ,  Chih-Fang Liu ,  Chih-Tang Peng ,  Tai-Chun Huang ,  Ryan Chia-Jen Chen

Inventor： Chia-Wei Chang ,  Chih-Fang Liu ,  Chih-Tang Peng ,  Tai-Chun Huang ,  Ryan Chia-Jen Chen

IPC: H01L29/78 ,  H01L21/306

CPC classification number: H01L21/3065 ,  H01L29/06 ,  H01L29/66795 ,  H01L29/7853

Abstract: A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin.

Abstract translation: FinFET器件可以包括横向邻近第二半导体鳍片的第一半导体鳍片。 第一半导体鳍片和第二半导体鳍片可以具有最小化缺陷和变形的轮廓。 第一半导体鳍片包括上部和下部。 第一半导体鳍片的下部可以具有在底部比第一半导体鳍片的上部更宽的扩张轮廓。 第二半导体散热片包括上部和下部。 第二半导体鳍片的下部可以具有比第二半导体鳍片的上部更宽但小于第一半导体鳍片的下部的扩口形状。

公开(公告)号：US08258588B2

公开(公告)日：2012-09-04

申请号：US12757241

申请日：2010-04-09

Applicant: Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

Inventor： Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/4983 ,  H01L29/6656

Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Abstract translation: 场效应晶体管的栅极结构的示例性结构包括栅电极; 栅电极下方的栅极绝缘体，在栅电极的相对侧具有基极区域; 以及在所述栅极结构的侧壁上的密封层，其中覆盖所述基底区域的所述密封层的下部的厚度小于所述栅极电极的侧壁上的所述密封层的上部的厚度，由此所述场效应晶体管 在基板表面几乎没有凹陷。

公开(公告)号：US08237231B2

公开(公告)日：2012-08-07

申请号：US13327992

申请日：2011-12-16

Applicant: Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L27/088

CPC classification number: H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer.

Abstract translation: 具有金属栅极结构的半导体结构包括具有第一栅极的第一型场效应晶体管，包括：基板上的高k电介质材料，高k电介质材料层上的第一金属层，具有第一功函数，以及 在第一金属层上的第一铝层。 第一铝层包括包含铝，氮和氧的界面层。 该器件还包括具有第二栅极的第二类场效应晶体管，其包括：衬底上的高k电介质材料，高k电介质材料层上的第二金属层，具有不同于第一功函数的第二功函数， 和在第二金属层上的第二铝层。

公开(公告)号：US20120164822A1

公开(公告)日：2012-06-28

申请号：US13408016

申请日：2012-02-29

Applicant: Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin

Inventor： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin

IPC: H01L21/28

CPC classification number: H01L21/823828 ,  H01L21/3221 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.

Abstract translation: 公开了制造具有高k /金属栅极特征的半导体器件的方法。 在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。 在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

公开(公告)号：US08163625B2

公开(公告)日：2012-04-24

申请号：US12753972

申请日：2010-04-05

Applicant: Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jr Jung Lin ,  Yu Chao Lin ,  Chih-Han Lin

Inventor： Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jr Jung Lin ,  Yu Chao Lin ,  Chih-Han Lin

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure having almost no divot. An exemplary method for fabricating an isolation structure, comprising: forming a pad oxide layer over a top surface of a substrate; forming an opening in the pad oxide layer, exposing a portion of the substrate; etching the exposed portion of the substrate, forming a trench in the substrate; filling the trench with an insulator; exposing a surface of the pad oxide layer and a surface of the insulator to a vapor mixture including at least an NH3 and a fluorine-containing compound; and heating the substrate at a temperature between 100° C. to 200° C.

Abstract translation: 本公开涉及集成电路制造，并且更具体地涉及具有几乎没有纹波的隔离结构的电子器件。 一种用于制造隔离结构的示例性方法，包括：在衬底的顶表面上形成衬垫氧化物层; 在所述衬垫氧化物层中形成开口，暴露所述衬底的一部分; 蚀刻衬底的暴露部分，在衬底中形成沟槽; 用绝缘体填充沟槽; 将衬垫氧化物层的表面和绝缘体的表面暴露于至少包含NH 3和含氟化合物的蒸汽混合物; 并在100℃至200℃的温度下加热基材。

公开(公告)号：US08153523B2

公开(公告)日：2012-04-10

申请号：US12362174

申请日：2009-01-29

Applicant: Ryan Chia-Jen Chen ,  Yi-Hsing Chen ,  Ching-Yu Chang

Inventor： Ryan Chia-Jen Chen ,  Yi-Hsing Chen ,  Ching-Yu Chang

IPC: H01L21/44

CPC classification number: H01L21/31111 ,  H01L21/31144 ,  H01L29/517

Abstract: A method of semiconductor fabrication including an etching process is provided. The method includes providing a substrate and forming a target layer on the substrate. An etchant layer is formed on the target layer. The etchant layer reacts with the target layer and etches a portion of the target layer. In an embodiment, an atomic layer of the target layer is etched. The etchant layer is then removed from the substrate. The process may be iterated any number of times to remove a desired amount of the target layer. In an embodiment, the method provides for decreased lateral etching. The etchant layer may provide for improved control in forming patterns in thin target layers such as, capping layers or high-k dielectric layers of a gate structure.

Abstract translation: 提供了包括蚀刻工艺的半导体制造方法。 该方法包括提供衬底并在衬底上形成目标层。 在目标层上形成蚀刻剂层。 蚀刻剂层与靶层反应并蚀刻目标层的一部分。 在一个实施例中，蚀刻目标层的原子层。 然后从衬底去除蚀刻剂层。 该过程可以迭代任何次数以去除期望量的目标层。 在一个实施例中，该方法提供减少的横向蚀刻。 蚀刻剂层可以提供在薄目标层中形成图案的改进控制，例如栅极结构的覆盖层或高k电介质层。

公开(公告)号：US08119473B2

公开(公告)日：2012-02-21

申请号：US12651017

申请日：2009-12-31

Applicant: Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L21/8232

CPC classification number: H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench.

Abstract translation: 本公开还提供了制造金属栅极叠层的方法的另一个实施例。 该方法包括在衬底上形成第一虚拟栅极和第二虚拟栅极; 从第一伪栅极去除多晶硅层，产生第一栅极沟槽; 在所述第一栅极沟槽中形成第一金属层和第一铝层; 对基材进行化学机械抛光（CMP）工艺; 使用含氮和氧的气体对所述第一铝层进行退火处理，在所述第一铝层上形成铝，氮和氧的界面层; 然后从第二伪栅极去除多晶硅层，产生第二栅极沟槽; 以及在所述第二栅极沟槽中的所述第二金属层上形成第二金属层和第二铝层。