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    HIGH DENSITY FLASH MEMORY DEVICE , CELL STRING FABRICATING METHOD THEREOF
    92.
    发明申请
    HIGH DENSITY FLASH MEMORY DEVICE , CELL STRING FABRICATING METHOD THEREOF 有权
    高密度闪存存储器件，其小型制造方法

    公开(公告)号：US20100038698A1

    公开(公告)日：2010-02-18

    申请号：US12312985

    申请日：2007-12-04

    Applicant: Jong-ho Lee

    Inventor： Jong-ho Lee

    IPC: H01L29/792

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: A flash memory cell string and a method of fabricating the same are provided. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially laminated on the semiconductor substrate. In each cell device, a source/drain region is not formed. The switching device does not include a source or drain region in a side connected to the cell devices. The switching device includes a source or drain region in the other side that is not connected to the cell devices. The source or drain region does or does not overlap the control electrode. Accordingly, it is possible to improve a miniaturization property and performance of NAND flash memory cell devices. If necessary, it is possible to electrically connect cells or cell strings by inducing an inversion layer through a fringing electric field from a control electrode.

    Abstract translation: 提供闪存单元串及其制造方法。 闪存单元串包括连接到单元设备的端部的多个单元设备和交换设备。 每个电池器件包括依次层压在半导体衬底上的半导体衬底，隧道绝缘层，电荷存储节点，控制绝缘层和控制电极。 在每个电池器件中，不形成源极/漏极区域。 开关器件不包括连接到电池器件的一侧的源极或漏极区域。 开关器件包括在另一侧中未连接到电池器件的源极或漏极区域。 源极或漏极区域与控制电极重叠或不重叠。 因此，可以提高NAND闪存单元装置的小型化性能和性能。 如果需要，可以通过从控制电极的边缘电场诱导反转层来电连接单元或单元串。

    Method of fabricating metal silicate layer using atomic layer deposition technique
    94.
    发明授权
    Method of fabricating metal silicate layer using atomic layer deposition technique 有权
    使用原子层沉积技术制造金属硅酸盐层的方法

    公开(公告)号：US07651729B2

    公开(公告)日：2010-01-26

    申请号：US11127748

    申请日：2005-05-12

    Applicant: Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

    Inventor： Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

    IPC: C23C16/00

    CPC classification number: C23C16/401 ,  C23C16/45529 ,  C23C16/45531

    Abstract: There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor. The silicon oxide layer formation cycle includes supplying a silicon source gas, exhausting the silicon source gas remaining in the reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.

    Abstract translation: 提供了使用原子层沉积技术在半导体衬底上制造金属硅酸盐层的方法。 所述方法包括至少一次执行金属硅酸盐层形成循环以形成具有所需厚度的金属硅酸盐层。 金属硅酸盐层形成循环包括重复进行金属氧化物层形成循环K次的操作和重复进行氧化硅层形成循环Q次的操作。 K和Q分别为1〜10的整数。 金属氧化物层形成循环包括将金属源气体供给到含有基板的反应器，排出留在反应器内的金属源气体，清洗反应器内部，然后向反应器供给氧化气体的工序。 氧化硅层形成循环包括提供硅源气体，排出留在反应器中的硅源气体以清洁反应器的内部，然后将氧化物气体供应到反应器中。

    Apparatus and method for canceling interference in multi-antenna system
    98.
    发明申请
    Apparatus and method for canceling interference in multi-antenna system 有权
    消除多天线系统干扰的装置和方法

    公开(公告)号：US20090147890A1

    公开(公告)日：2009-06-11

    申请号：US12315342

    申请日：2008-12-02

    Applicant: Joo-Hyun Lee ,  Suk-Seung Hwang ,  Jong-Ho Lee ,  Soong-Yoon Choi

    Inventor： Joo-Hyun Lee ,  Suk-Seung Hwang ,  Jong-Ho Lee ,  Soong-Yoon Choi

    IPC: H04L1/02 ,  H03D1/00

    CPC classification number: H04L1/0048 ,  H04B7/0851 ,  H04L1/0054 ,  H04L25/0204 ,  H04L25/03171

    Abstract: An apparatus and a method for canceling interference based on Maximum Likelihood (ML) at a receiver of a multi-antenna system are provided. The method includes estimating a channel using a signal received over one or more receiver antennas; generating one or more weights using the estimated channel to cancel interference; detecting a candidate symbol having the shortest Euclidean distance through Maximum Likelihood using a first weight; and soft-decoding the candidate symbol using a second weight. Therefore, by receiving the signal based on the ML under the interference, the system capacity can be increased and the reception performance can be enhanced.

    Abstract translation: 提供了一种用于在多天线系统的接收机处基于最大似然（ML）消除干扰的装置和方法。 该方法包括使用在一个或多个接收机天线上接收的信号来估计信道; 使用所估计的信道生成一个或多个权重以消除干扰; 使用第一权重通过最大似然检测具有最短欧几里德距离的候选符号; 以及使用第二权重对候选符号进行软解码。 因此，通过在干扰下接收基于ML的信号，可以提高系统容量并提高接收性能。

    One-transistor floating-body dram cell device with non-volatile function
    99.
    发明申请
    One-transistor floating-body dram cell device with non-volatile function 有权
    具有非易失性功能的单晶体体浮体电容器

    公开(公告)号：US20090147580A1

    公开(公告)日：2009-06-11

    申请号：US12292427

    申请日：2008-11-19

    Applicant: Jong-Ho Lee

    Inventor： Jong-Ho Lee

    IPC: G11C16/04 ,  H01L27/108 ,  G11C16/06

    CPC classification number: H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/42332 ,  H01L29/792

    Abstract: Disclosed herein is a one-transistor (1T) floating-body Dynamic Random Access Memory (DRAM) cell device with a non-volatile function for implementing the high integration/high performance DRAM. The 1T floating-body DRAM cell device includes a floating body for storing information of the DRAM cell device, a source and a drain formed on respective sides of the floating body, a gate insulating layer formed on a top of the floating body, a gate electrode formed on a top of the gate insulating layer, a gate stack formed under the floating body and configured to have a charge storage node for storing electric charges, and a control electrode formed on a lower side of the gate stack or partially or completely surrounded by the gate stack. The DRAM cell device performs “write0” and “write1” operations or a read operation. The DRAM cell device performs a non-volatile program operation or a non-volatile erase operation.

    Abstract translation: 本文公开了具有用于实现高集成/高性能DRAM的非易失性功能的单晶体管（1T）浮体动态随机存取存储器（DRAM）单元装置。 1T浮体DRAM单元装置包括用于存储DRAM单元装置的信息的浮动体，形成在浮体的各侧的源极和漏极，形成在浮体顶部的栅极绝缘层，栅极 形成在所述栅极绝缘层的顶部上的电极，形成在所述浮体下方并且被配置为具有用于存储电荷的电荷存储节点的栅极堆叠;以及形成在所述栅极堆叠的下侧或部分地或完全被包围的控制电极 由门堆栈。 DRAM单元装置执行“write0”和“write1”操作或读操作。 DRAM单元装置执行非易失性编程操作或非易失性擦除操作。

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