公开(公告)号：US08533522B2

公开(公告)日：2013-09-10

申请号：US13624487

申请日：2012-09-21

Applicant: MOSAID Technologies Incorporated

Inventor： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC: G06F1/12

CPC classification number: G06F5/08

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract translation: 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

公开(公告)号：US20130215799A1

公开(公告)日：2013-08-22

申请号：US13754366

申请日：2013-01-30

Applicant: MOSAID Technologies Incorporated

Inventor： Yehuda BINDER

IPC: H04L5/14

CPC classification number: H04L5/14 ,  H04B3/54 ,  H04B3/542 ,  H04B2203/5437 ,  H04B2203/5445 ,  H04B2203/545 ,  H04B2203/5458 ,  H04L12/2801 ,  H04L12/2803 ,  H04L12/2838 ,  H04L29/0602 ,  H04L43/00 ,  H04L2012/2843 ,  H04L2012/2845 ,  H04M19/02 ,  Y10S370/908

Abstract: A serial intelligent cell (SIC) and a connection topology for local area networks using Electrically-conducting media. A local area network can be configured from a plurality of SIC's interconnected so that all communications between two adjacent SIC's is both point-to-point and bidirectional. Each SIC can be connected to one or more other SIC's to allow redundant communication paths. Communications in different areas of a SIC network are independent of one another, so that there is no fundamental limit on the size or extent of a SIC network. Each SIC can optionally be connected to one or more data terminals, computers, telephones, sensors, actuators, etc., to facilitate interconnectivity among such devices. Networks according to the present invention can be configured for a variety of applications, including a local telephone system, remote computer bus extender, multiplexers, PABX/PBX functionality, security systems, and local broadcasting services.

公开(公告)号：US20130215677A1

公开(公告)日：2013-08-22

申请号：US13860724

申请日：2013-04-11

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  Peter B. Gillingham ,  William F. Petrie

IPC: G11C13/00

CPC classification number: G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C2029/0411 ,  G11C2211/5647

Abstract: A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data value or the inversion of the data value. In one embodiment an odd number of set polarity bits indicates that the data bits represent the inversion of the data value and an even number of set polarity bits indicates that the data bits represent the data value. The PCM apparatus has enhanced endurance and improved error tolerance.

Abstract translation: 一种相变存储器（PCM）装置，包括用于存储表示数据值的数据位或数据值反转的数据位的数据场，以及用于存储用于指示存储在数据中的数据位的多个极性位的极性场 字段表示数据值或数据值的反转。 在一个实施例中，奇数个设置极性位指示数据位表示数据值的反转，偶数个设置的极性位表示数据位表示数据值。 PCM装置具有增强的耐久性和改进的误差容限。

公开(公告)号：US20130176043A1

公开(公告)日：2013-07-11

申请号：US13784361

申请日：2013-03-04

Applicant: MOSAID Technologies Incorporated

Inventor： Ami HAZANI ,  Yehuda BINDER

IPC: G01R27/02

CPC classification number: G01R27/02 ,  G01R27/04

Abstract: A system and method for measuring a characteristic impedance of a transmission-line comprises transmitting energy to the line, and shortly after measuring the voltage/current involved and thus measuring the equivalent impedance. The measured characteristic impedance may then be used in order to determine the termination value required to minimize reflections. In another embodiment, the proper termination is set or measured by adjusting the termination value to achieve maximum power dissipation in the terminating device. The equivalent characteristic impedance measurement may be used to count the number of metallic conductors connected to a single connection point. This abstract is not intended to limit or construe the scope of the claims.

Abstract translation: 用于测量传输线的特性阻抗的系统和方法包括向线路传输能量，以及在测量所涉及的电压/电流后不久测量等效阻抗。 然后可以使用测量的特性阻抗，以便确定使反射最小化所需的终止值。 在另一个实施例中，通过调整终端值来设置或测量适当的终端以实现终端设备中的最大功率消耗。 可以使用等效特征阻抗测量来计数连接到单个连接点的金属导体的数量。 本摘要并不旨在限制或解释权利要求的范围。

公开(公告)号：US20130134607A1

公开(公告)日：2013-05-30

申请号：US13687198

申请日：2012-11-28

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM

IPC: H01L23/52

CPC classification number: H01L23/52 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device is disclosed, comprising a substrate having at least one substrate bonding pad. A plurality of semiconductor dies are stacked on the substrate. Each semiconductor die has at least one die bonding pad located on an active surface of the die. A plurality of interposers are each mounted on a corresponding one of the semiconductor dies. Each interposer has an aperture formed therethrough in alignment with the at least one die bonding pad. An electrical connection between the at least one die bonding pad and the at least one substrate bonding pad is formed at least in part by the interposer. The electrical connection includes at least one wire bond.

Abstract translation: 公开了一种半导体器件，包括具有至少一个衬底接合焊盘的衬底。 多个半导体管芯被堆叠在基板上。 每个半导体管芯具有位于管芯的有效表面上的至少一个管芯接合焊盘。 多个插入件分别安装在相应的一个半导体管芯上。 每个插入器具有与至少一个管芯接合焊盘对准的通孔形成的孔。 所述至少一个管芯接合焊盘和所述至少一个衬底接合焊盘之间的电连接至少部分地由所述插入件形成。 电连接包括至少一个引线接合。

公开(公告)号：US20130070539A1

公开(公告)日：2013-03-21

申请号：US13650580

申请日：2012-10-12

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM ,  HakJune OH

IPC: G11C11/402 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

公开(公告)号：US20030223259A1

公开(公告)日：2003-12-04

申请号：US10158196

申请日：2002-05-31

Applicant: Mosaid Technologies Incorporated

Inventor： Alan Roth

IPC: G11C015/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract translation: 一种用于使用可变宽度搜索数据执行搜索操作的内容可寻址存储器（CAM），所述CAM包括多个CAM单元阵列，每个阵列耦合到相应的子搜索数据总线，所述子搜索总线被限制为形成主 搜索数据总线，应用搜索数据; 接收来自相应CAM阵列的匹配线信号的选择器电路，匹配线信号表示在相关联的CAM阵列中形成的搜索和比较的结果，选择器电路响应于选择一个或多个所述匹配的模式选择信号 线路输出信号被切换到优先编码器和多重匹配解算器（PE-MMR），其中在第一模式中，匹配线输出信号被切换到所述PE-MMR，并且在第二模式中，来自所选择的匹配线输出信号组 阵列被切换到所述PE-MMR。

公开(公告)号：US20010009518A1

公开(公告)日：2001-07-26

申请号：US09819488

申请日：2001-03-28

Applicant: MOSAID Technologies Incorporated

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Robert F. Harland ,  Valerie L. Lines

IPC: H02M003/18

CPC classification number: G11C5/145 ,  G05F3/205 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085 ,  H02M3/07

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by Vtn as in the prior art. The boosting capacitors are charged by Vdd, thus eliminating drift tracking problems associated with clock boosting sources and Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract translation: 用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。 升压电路中的晶体管完全切换，消除了如现有技术中Vtn的升压电压的降低。 升压电容由Vdd充电，从而消除与时钟增压源和Vdd相关的漂移跟踪问题。 调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

公开(公告)号：US20230384935A1

公开(公告)日：2023-11-30

申请号：US18303127

申请日：2023-04-19

Applicant: Mosaid Technologies Incorporated

Inventor： Peter B. Gillingham ,  Graham Allan

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00

CPC classification number: G06F3/061 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/0483 ,  G06F3/0655 ,  G06F3/0688 ,  G11C14/0018 ,  H03K2005/00247

Abstract: A clock mode configuration circuit for a memory device. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

公开(公告)号：US20230268447A1

公开(公告)日：2023-08-24

申请号：US18305537

申请日：2023-04-24

Applicant: Mosaid Technologies Incorporated

Inventor： Hyoung Seub RHIE

IPC: H01L29/792 ,  H01L29/66 ,  G11C16/04 ,  G11C11/56 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L29/7926 ,  G11C11/5621 ,  G11C16/0483 ,  H01L29/66833 ,  H10B43/27 ,  H10B43/40 ,  G11C2213/71

Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.