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    Methods of forming integrated circuit devices having tensile and compressive stress layers therein and devices formed thereby
    91.
    发明授权
    Methods of forming integrated circuit devices having tensile and compressive stress layers therein and devices formed thereby 有权
    形成其中具有拉伸和压应力层的集成电路器件的方法以及由此形成的器件

    公开(公告)号：US07785951B2

    公开(公告)日：2010-08-31

    申请号：US11831223

    申请日：2007-07-31

    Applicant: Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    Inventor： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    IPC: H01L21/8238

    CPC classification number: H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

    Abstract: Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

    Abstract translation: 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

    Semiconductor device and method of fabricating the same
    92.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07759185B2

    公开(公告)日：2010-07-20

    申请号：US11853187

    申请日：2007-09-11

    Applicant: Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

    Inventor： Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.

    Abstract translation: 半导体器件包括覆盖第一栅电极的第一应力膜和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅电极的至少一部分，覆盖第二栅电极的第二应力膜和第二应力膜 第二晶体管区域的源极/漏极区域，并且与界面区域的第三栅电极上的第一应力膜的至少一部分重叠，以及形成在第一和第二应力膜上的层间绝缘膜。 半导体器件还包括多个通过层间绝缘膜形成的第一接触孔和第一晶体管区域中的第一应力膜，以暴露第一栅极电极和第一源极/漏极区域，形成多个第二接触孔 层间绝缘膜和第二晶体管区域中的第二应力膜，以暴露第二栅电极和第二源极/漏极区，以及通过层间绝缘膜，第二应力膜和第一应力膜形成的第三接触孔 暴露第三栅电极的界面区域。 形成第三接触孔的第三栅电极的上侧的凹部的深度等于或大于第一栅电极的上侧的凹部的深度，其中第一接触孔 形成了。

    Method of fabricating semiconductor integrated circuit device
    93.
    发明申请
    Method of fabricating semiconductor integrated circuit device 审中-公开
    制造半导体集成电路器件的方法

    公开(公告)号：US20100173497A1

    公开(公告)日：2010-07-08

    申请号：US12655837

    申请日：2010-01-06

    Applicant: Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Seo-Woo Nam ,  In-Keun Lee ,  Jung-Hoon Lee

    Inventor： Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Seo-Woo Nam ,  In-Keun Lee ,  Jung-Hoon Lee

    IPC: H01L21/306

    CPC classification number: H01L21/32139

    Abstract: A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the second etching on the first pattern and the remaining portion of second pattern of the intermediate mask pattern and forming a final mask pattern; and patterning the layer to be etched using the final mask pattern.

    Abstract translation: 制造半导体集成电路器件的方法包括：提供衬底; 在基板上依次形成被蚀刻层，第一层和第二层; 在所述第一层和第二层上形成第一蚀刻掩模，所述第一蚀刻掩模具有以第一间距彼此分开并沿第一方向延伸的多个第一线图案; 使用第一蚀刻掩模在第二层和第一层上顺序地执行第一蚀刻以形成具有第二和第一图案的中间掩模图案; 在所述中间掩模图案上形成第二蚀刻掩模，所述第二蚀刻掩模包括以第二间距彼此分开并沿除了所述第一方向之外的第二方向延伸的多个第二线图案; 在第二图案的一部分上使用第二蚀刻掩模进行第二蚀刻，使得第二图案的剩余部分留在第一图案上; 在与第一图案上的第二蚀刻和中间掩模图案的第二图案的剩余部分不同的条件下，使用第二蚀刻掩模进行第三蚀刻，并形成最终的掩模图案; 并使用最终的掩模图案来图案化待蚀刻的层。

    CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same
    94.
    发明授权
    CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same 有权
    具有埋入硅锗层的CMOS集成电路器件和衬底及其形成方法

    公开(公告)号：US07642140B2

    公开(公告)日：2010-01-05

    申请号：US11656717

    申请日：2007-01-23

    Applicant: Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

    Inventor： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

    IPC: H01L21/84

    CPC classification number: H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

    Abstract: CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2

    Abstract translation: CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si1-xGex层也设置在电绝缘层和未应变硅有源层之间。 Si1-xGex层与未应变的硅有源层形成第一结，并且其中Ge的分级浓度在从峰值电平朝向未应变硅有源层的表面延伸的第一方向上单调减小。 峰值Ge浓度水平大于x = 0.15，并且Si1-xGex层中的Ge浓度在第一结处从峰值水平变化到小于约x = 0.1的水平。 Ge在第一结处的浓度可能是突然的。 更优选地，Si1-xGex层中的Ge的浓度从0.2

    Methods of Forming Integrated Circuit Devices Having Tensile and Compressive Stress Layers Therein and Devices Formed Thereby
    99.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Tensile and Compressive Stress Layers Therein and Devices Formed Thereby 有权
    形成具有拉伸和压缩应力层的集成电路器件的方法和由此形成的器件

    公开(公告)号：US20080081476A1

    公开(公告)日：2008-04-03

    申请号：US11831223

    申请日：2007-07-31

    Applicant: Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    Inventor： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    IPC: H01L21/302 ,  H01L21/31

    CPC classification number: H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

    Abstract: Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

    Abstract translation: 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

    SEMICONDUCTOR DEVICES INCLUDING MULTIPLE STRESS FILMS IN INTERFACE AREA AND METHODS OF PRODUCING THE SAME
    100.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING MULTIPLE STRESS FILMS IN INTERFACE AREA AND METHODS OF PRODUCING THE SAME 失效
    在界面中包括多个应力膜的半导体器件及其生产方法

    公开(公告)号：US20080079087A1

    公开(公告)日：2008-04-03

    申请号：US11851500

    申请日：2007-09-07

    Applicant: Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    Inventor： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    IPC: H01L29/78 ,  H01L21/8238

    CPC classification number: H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

    Abstract translation: 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

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