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119 条记录 (耗时 0.038 秒)

    Method for forming copper fuse links
    91.
    发明申请
    Method for forming copper fuse links 有权
    形成铜熔丝的方法

    公开(公告)号：US20050189612A1

    公开(公告)日：2005-09-01

    申请号：US10791606

    申请日：2004-03-01

    申请人： Meng-Chi Hung ,  Hao-Yi Tsai ,  Shang-Yun Hou

    发明人： Meng-Chi Hung ,  Hao-Yi Tsai ,  Shang-Yun Hou

    IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/768 ,  H01L23/525 ,  H01L29/00

    CPC分类号： H01L23/5256 ,  H01L21/76807 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved fuse link structure and method of forming the same, the method including forming a dual damascene structure by a trench-first process to form a dual damascene having a relatively thinner fuse link portion spanning an area between and overlying fuse metal interconnect structures including a mechanically robust dielectric insulating layer portion underlying the relatively thinner fuse link portion.

    摘要翻译： 一种改进的熔断体结构及其形成方法，所述方法包括通过沟槽第一工艺形成双镶嵌结构，以形成具有相对较薄的熔断体部分的双镶嵌件，跨部分熔合金属互连结构之间的区域包括 在相对较薄的熔断体部分下面的机械坚固的介电绝缘层部分。

    Calibration Kits for RF Passive Devices
    93.
    发明申请
    Calibration Kits for RF Passive Devices 有权
    RF被动设备的校准套件

    公开(公告)号：US20130332092A1

    公开(公告)日：2013-12-12

    申请号：US13491364

    申请日：2012-06-07

    申请人： Jie Chen ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo

    发明人： Jie Chen ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo

    IPC分类号： G06F19/00 ,  G06F17/50 ,  H01L23/48

    CPC分类号： H01L23/66 ,  G01R1/07328 ,  G01R35/005 ,  G06F17/5009 ,  H01L21/76822 ,  H01L22/34 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/13 ,  H01L28/10 ,  H01L2223/6627 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/19011 ,  H01L2924/1903 ,  H01L2924/19042 ,  H01L2924/00014 ,  H01L2924/014

    摘要： A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.

    摘要翻译： 一种方法包括测量晶片中的第一校准套件以获得第一性能数据。 晶片包括衬底，以及在衬底上的多个电介质层。 第一校准套件包括多个电介质层上的第一无源器件，其中在多个电介质层中基本上没有金属特征被布置在第一无源器件中。 该方法还包括测量晶片中的第二校准套件以获得第二性能数据。 第二校准套件包括与第一器件相同并且在多个电介质层上相同的第二无源器件，以及多个电介质层中的虚设图案并且被第二无源器件重叠。 第一性能数据和第二性能数据被去嵌入以确定多个介电层中的金属图案对覆盖无源器件的影响。

    Structure for reducing integrated circuit corner peeling
    95.
    发明授权
    Structure for reducing integrated circuit corner peeling 有权
    减少集成电路拐角剥离的结构

    公开(公告)号：US08373254B2

    公开(公告)日：2013-02-12

    申请号：US12181663

    申请日：2008-07-29

    申请人： Hsien-Wei Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai

    发明人： Hsien-Wei Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai

    IPC分类号： H01L21/302 ,  H01L23/58

    CPC分类号： H01L23/49811 ,  H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers.

    摘要翻译： 公开了一种减少集成电路角剥离并减少开裂的防裂结构。 防裂结构包括半导体衬底; 设置在所述半导体衬底上的第一材料的第一多个电介质层; 设置在所述第一多个电介质层上的第二材料的不同于所述第一材料的第二多个电介质层，其中所述第一多个电介质层和所述第二多个电介质层在界面处相交; 以及通过所述第一多个介电层和所述第二多个电介质层的界面形成的多个金属结构体和多个通孔结构。

    Semiconductor wafer with protection structure against damage during a die separation process
    97.
    发明申请
    Semiconductor wafer with protection structure against damage during a die separation process 审中-公开
    具有保护结构的半导体晶片在模具分离过程中不受损坏

    公开(公告)号：US20060125059A1

    公开(公告)日：2006-06-15

    申请号：US11012760

    申请日：2004-12-15

    申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Shih-Hsun Hsu ,  Bai-Yao Lou

    发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Shih-Hsun Hsu ,  Bai-Yao Lou

    IPC分类号： H01L23/544

    CPC分类号： H01L23/544 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor wafer includes one or more dies, each of which has a boundary surrounding an integrated circuitry for separating one from another. One or more pattern units are disposed adjacent to the die for monitoring a fabrication process thereof. A protection structure is disposed between the die and the pattern units for preventing the die from damage during a separation of the die from the semiconductor wafer. Thus, the semiconductor wafer is adapted to prevent damage during a die separation process.

    摘要翻译： 半导体晶片包括一个或多个管芯，每个管芯具有围绕用于彼此分离的集成电路的边界。 一个或多个图案单元设置成与模具相邻以用于监视其制造工艺。 保护结构设置在模具和图案单元之间，用于防止模具在与半导体晶片分离期间损坏。 因此，半导体晶片适于防止在模具分离过程中的损坏。

    Increasing dielectric constant in local regions for the formation of capacitors
    99.
    发明授权
    Increasing dielectric constant in local regions for the formation of capacitors 有权
    在局部区域增加介电常数以形成电容器

    公开(公告)号：US07553736B2

    公开(公告)日：2009-06-30

    申请号：US11486891

    申请日：2006-07-13

    申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen

    发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen

    IPC分类号： H01L21/20

    CPC分类号： H01L21/31058

    摘要： A method for increasing capacitances of capacitors and the resulting integrated structure are provided. The method includes providing a substrate, forming a low-k dielectric layer over the substrate wherein the low-k dielectric layer includes a capacitor region and a non-capacitor region, forming a capacitor in the capacitor region, forming a masking layer which masks the non-capacitor region while leaving the capacitor region exposed, performing a local treatment to increase a k value of the low-k dielectric layer in the capacitor region, and removing the masking layer.

    摘要翻译： 提供了一种用于增加电容器的电容的方法和所得到的集成结构。 该方法包括提供衬底，在衬底上形成低k电介质层，其中低k电介质层包括电容器区域和非电容器区域，在电容器区域中形成电容器，形成屏蔽层 非电容器区域，同时使电容器区域露出，进行局部处理以增加电容器区域中的低k电介质层的ak值，并且去除掩模层。

    Increasing dielectric constant in local regions for the formation of capacitors
    100.
    发明申请
    Increasing dielectric constant in local regions for the formation of capacitors 有权
    在局部区域增加介电常数以形成电容器

    公开(公告)号：US20080014706A1

    公开(公告)日：2008-01-17

    申请号：US11486891

    申请日：2006-07-13

    申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen

    发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen

    IPC分类号： H01L21/20

    CPC分类号： H01L21/31058

    摘要： A method for increasing capacitances of capacitors and the resulting integrated structure are provided. The method includes providing a substrate, forming a low-k dielectric layer over the substrate wherein the low-k dielectric layer includes a capacitor region and a non-capacitor region, forming a capacitor in the capacitor region, forming a masking layer which masks the non-capacitor region while leaving the capacitor region exposed, performing a local treatment to increase a k value of the low-k dielectric layer in the capacitor region, and removing the masking layer.

    摘要翻译： 提供了一种用于增加电容器的电容的方法和所得到的集成结构。 该方法包括提供衬底，在衬底上形成低k电介质层，其中低k电介质层包括电容器区域和非电容器区域，在电容器区域中形成电容器，形成屏蔽层 非电容器区域，同时使电容器区域露出，进行局部处理以增加电容器区域中的低k电介质层的ak值，并且去除掩模层。