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39 条记录 (耗时 0.033 秒)

    Calibration Kits for RF Passive Devices
    4.
    发明申请
    Calibration Kits for RF Passive Devices 有权
    RF被动设备的校准套件

    公开(公告)号：US20130332092A1

    公开(公告)日：2013-12-12

    申请号：US13491364

    申请日：2012-06-07

    申请人： Jie Chen ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo

    发明人： Jie Chen ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo

    IPC分类号： G06F19/00 ,  G06F17/50 ,  H01L23/48

    CPC分类号： H01L23/66 ,  G01R1/07328 ,  G01R35/005 ,  G06F17/5009 ,  H01L21/76822 ,  H01L22/34 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/13 ,  H01L28/10 ,  H01L2223/6627 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/19011 ,  H01L2924/1903 ,  H01L2924/19042 ,  H01L2924/00014 ,  H01L2924/014

    摘要： A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.

    摘要翻译： 一种方法包括测量晶片中的第一校准套件以获得第一性能数据。 晶片包括衬底，以及在衬底上的多个电介质层。 第一校准套件包括多个电介质层上的第一无源器件，其中在多个电介质层中基本上没有金属特征被布置在第一无源器件中。 该方法还包括测量晶片中的第二校准套件以获得第二性能数据。 第二校准套件包括与第一器件相同并且在多个电介质层上相同的第二无源器件，以及多个电介质层中的虚设图案并且被第二无源器件重叠。 第一性能数据和第二性能数据被去嵌入以确定多个介电层中的金属图案对覆盖无源器件的影响。

    WAFER LEVEL CONFORMAL COATING FOR LED DEVICES
    6.
    发明申请
    WAFER LEVEL CONFORMAL COATING FOR LED DEVICES 有权
    用于LED器件的WAFER LEVEL CONFORMAL COATING

    公开(公告)号：US20120129282A1

    公开(公告)日：2012-05-24

    申请号：US12951662

    申请日：2010-11-22

    申请人： Hsing-Kuo Hsia ,  Chih-Kuang Yu ,  Hung-Yi Kuo ,  Hung-Wen Huang

    发明人： Hsing-Kuo Hsia ,  Chih-Kuang Yu ,  Hung-Yi Kuo ,  Hung-Wen Huang

    IPC分类号： H01L33/52

    CPC分类号： H01L33/50 ,  H01L2933/0041 ,  H01L2933/005

    摘要： Provided is a method of fabricating a light-emitting diode (LED) device. The method includes providing a wafer. The wafer has light-emitting diode (LED) devices formed thereon. The method includes immersing the wafer into a polymer solution that has a surface tension lower than that of acetic acid. The polymer solution contains a liquid polymer and phosphor particles. The method includes lifting the wafer out of the polymer solution at a substantially constant speed. The method includes drying the wafer. The above processes form a conformal coating layer at least partially around the LED devices. The coating layer includes the phosphor particles. The coating layer also has a substantially uniform thickness.

    摘要翻译： 提供一种制造发光二极管（LED）装置的方法。 该方法包括提供晶片。 晶片具有形成在其上的发光二极管（LED）装置。 该方法包括将晶片浸入表面张力低于乙酸的聚合物溶液中。 聚合物溶液含有液体聚合物和磷光体颗粒。 该方法包括以基本恒定的速度将晶片提出聚合物溶液。 该方法包括干燥晶片。 上述方法至少部分地围绕LED器件形成保形涂层。 涂层包括荧光体颗粒。 涂层也具有基本均匀的厚度。

    LED DEVICE WITH IMPROVED THERMAL PERFORMANCE
    7.
    发明申请
    LED DEVICE WITH IMPROVED THERMAL PERFORMANCE 有权
    具有改进的热性能的LED器件

    公开(公告)号：US20120119228A1

    公开(公告)日：2012-05-17

    申请号：US12944895

    申请日：2010-11-12

    申请人： Hsing-Kuo Hsia ,  Chih-Kuang Yu ,  Hung-Yi Kuo ,  Chyi Shyuan Chern

    发明人： Hsing-Kuo Hsia ,  Chih-Kuang Yu ,  Hung-Yi Kuo ,  Chyi Shyuan Chern

    IPC分类号： H01L33/00

    CPC分类号： H01L33/64 ,  H01L25/075 ,  H01L33/54 ,  H01L33/58 ,  H01L33/641 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

    摘要： An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.

    摘要翻译： 一种装置包括其中具有多个开口的晶片。 对于每个开口，LED器件以这样的方式耦合到导电载体和晶片，使得每个耦合的LED器件和导电载体的一部分至少部分地填充开口。 制造LED器件的方法包括在晶片中形成多个开口。 该方法还包括将发光二极管（LED）器件耦合到导电载体上。 具有导电载体的LED装置至少部分地填充每个开口。

    Chipsets and clock generation methods thereof
    8.
    发明授权
    Chipsets and clock generation methods thereof 有权
    芯片组及其时钟生成方法

    公开(公告)号：US07671645B2

    公开(公告)日：2010-03-02

    申请号：US12102119

    申请日：2008-04-14

    申请人： Chia-Hung Su ,  Hung-Yi Kuo

    发明人： Chia-Hung Su ,  Hung-Yi Kuo

    IPC分类号： H03L7/06

    CPC分类号： H03L7/14 ,  H03L7/18

    摘要： Chipsets capable of preventing malfunction caused by feedback clock distortion are provided, in which a phase frequency detector generates a control voltage according to a first reference clock and a first feedback clock, a voltage-controlled oscillator generates an output clock according to the control voltage, a frequency divider performs a frequency-division on a second feedback clock to obtain the first feedback clock, and a frequency filter estimates swings and frequency of a third feedback clock from an external unit and selectively outputs one of the third feedback clock or the output clock to serve as the second clock.

    摘要翻译： 提供能够防止由反馈时钟失真引起的故障的芯片组，其中相位频率检测器根据第一参考时钟和第一反馈时钟产生控制电压，压控振荡器根据控制电压产生输出时钟， 分频器对第二反馈时钟进行分频以获得第一反馈时钟，频率滤波器从外部单元估计第三反馈时钟的摆动和频率，并选择性地输出第三反馈时钟或输出时钟之一 作为第二个时钟。

    Method and related apparatus for calibrating signal driving parameters between chips
    9.
    发明授权
    Method and related apparatus for calibrating signal driving parameters between chips 有权
    用于校准芯片之间的信号驱动参数的方法和相关装置

    公开(公告)号：US07587651B2

    公开(公告)日：2009-09-08

    申请号：US11161614

    申请日：2005-08-10

    申请人： Hung-Yi Kuo ,  Jenny Chen

    发明人： Hung-Yi Kuo ,  Jenny Chen

    IPC分类号： G01R31/30 ,  G06F11/00

    CPC分类号： G06F13/4269

    摘要： A calibrating method for adjusting related parameters when a first chip and a second chip switch signals is disclosed. The calibrating method includes: utilizing the first chip to output a test signal through using a first driving force in order to represent a test value; utilizing the second chip to receive the test signal and utilizing the second chip to read the test signal to determine a value; and performing a comparison step for comparing the value with the test value to detect whether said value complies with the test value.

    摘要翻译： 一种当第一芯片和第二芯片开关信号被公开时用于调整相关参数的校准方法。 校准方法包括：利用第一芯片通过使用第一驱动力来输出测试信号以便表示测试值; 利用第二芯片接收测试信号并利用第二芯片读取测试信号以确定值; 以及执行用于将所述值与所述测试值进行比较的比较步骤，以检测所述值是否符合所述测试值。

    Timing adjustment circuit and method thereof
    10.
    发明授权
    Timing adjustment circuit and method thereof 有权
    定时调整电路及其方法

    公开(公告)号：US07375561B2

    公开(公告)日：2008-05-20

    申请号：US11515850

    申请日：2006-09-06

    申请人： Hung-Yi Kuo ,  Hui-Mei Chen

    发明人： Hung-Yi Kuo ,  Hui-Mei Chen

    IPC分类号： H03L7/00

    CPC分类号： H03L7/06 ,  H04L7/0004 ,  H04L7/0337

    摘要： A timing adjustment circuit and method thereof are disclosed. The timing adjustment circuit at least consists of a second timing adjustment unit, a multistage sample circuit, and a decision circuit for adjusting received timing of an output signal transmitted by a first chip and received by a second chip. The method takes advantage of the multistage sample circuit to receive a clock signal of receiving end so as to generate a plurality of sample clock signal. Later, according to the sample clock signals, sample output signals to generate a plurality of sampled signal. At last, make comparison of the sampled signals by the decision circuit in accordance with the output signals to generate a second adjustment signal being transmitted to the second timing adjustment unit for adjusting phase of a base clock to generate an adjusted receiving-end clock signal. Thus the receiving timing of the second chip to receive the output signal is adjusted. Moreover, the decision circuit sends a first adjustment signal to a first timing adjustment unit of the timing adjustment circuit for generating an adjusted output-end clock signal. Thus the output timing that the first chip transmits the output signal to the second chip is adjusted.

    摘要翻译： 公开了一种定时调整电路及其方法。 定时调整电路至少包括第二定时调整单元，多级采样电路和用于调整由第一芯片发送并由第二芯片接收的输出信号的接收定时的判定电路。 该方法利用多级采样电路来接收接收端的时钟信号，以产生多个采样时钟信号。 之后，根据采样时钟信号，采样输出信号产生多个采样信号。 最后，根据输出信号，通过判定电路对取样信号进行比较，生成正被发送到第二定时调整单元的第二调整信号，以调整基本时钟的相位，生成经调整的接收端时钟信号。 因此，调整第二芯片接收输出信号的接收定时。 此外，判定电路将第一调整信号发送到定时调整电路的第一定时调整单元，以产生经调整的输出端时钟信号。 因此，调整第一芯片将输出信号传送到第二芯片的输出定时。