利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

144 条记录 (耗时 0.038 秒)

    APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRAYS AND ASSOCIATED METHODS
    91.
    发明申请
    APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRAYS AND ASSOCIATED METHODS 有权
    改进现场可编程门阵列性能的方法及相关方法

    公开(公告)号：US20130043902A1

    公开(公告)日：2013-02-21

    申请号：US13214144

    申请日：2011-08-19

    申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

    发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17784 ,  H03K19/17792

    摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

    摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出针对 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。

    Phase-locked loop architecture and clock distribution system
    92.
    发明授权
    Phase-locked loop architecture and clock distribution system 有权
    锁相环架构和时钟分配系统

    公开(公告)号：US08228102B1

    公开(公告)日：2012-07-24

    申请号：US12717062

    申请日：2010-03-03

    申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

    发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

    IPC分类号： H03L7/06

    CPC分类号： H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

    摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条 侧。 可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。 另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。 每个PMA三元组模块包括第一，第二和第三通道。 第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。 还公开了其它实施例和特征。

    Reducing false positives in configuration error detection for programmable devices
    93.
    发明授权
    Reducing false positives in configuration error detection for programmable devices 有权
    减少可编程器件配置错误检测中的误报

    公开(公告)号：US07620876B2

    公开(公告)日：2009-11-17

    申请号：US11407519

    申请日：2006-04-19

    申请人： David Lewis ,  Robert Blake ,  Richard G. Cliff ,  Srinivas T. Reddy

    发明人： David Lewis ,  Robert Blake ,  Richard G. Cliff ,  Srinivas T. Reddy

    IPC分类号： G11C29/00

    CPC分类号： G11C29/42 ,  G06F11/1008 ,  G11C29/52

    摘要： A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data indicates unused portions of the memory. Unused portions of the memory may correspond with configuration data for unused portions of a programmable device. Each bit of the sensitivity mask data may indicate the usage of one or more bits of the data from the memory. In response to the mask data, the masking unit sets data from the unused portions of the memory to values that do not change the result of the error detection computations. This prevents any errors in data from the unused portions of the memory from raising an error signal.

    摘要翻译： 设备通过使用掩蔽单元和灵敏度掩码数据来减少假阳性存储器错误检测，以从错误检测计算中排除存储器的未使用部分。 一种设备包括一个错误检测单元，用于从存储器读取数据并验证数据完整性。 灵敏度掩码数据指示存储器的未使用部分。 存储器的未使用部分可以对应于可编程设备的未使用部分的配置数据。 灵敏度掩码数据的每一位可以指示来自存储器的数据的一位或多位的使用。 响应于掩模数据，掩蔽单元将来自存储器的未使用部分的数据设置为不改变错误检测计算结果的值。 这防止来自存储器的未使用部分的数据中的任何错误引起错误信号。

    Tristate structures for programmable logic devices
    95.
    发明授权
    Tristate structures for programmable logic devices 失效
    可编程逻辑器件的三态结构

    公开(公告)号：US06882177B1

    公开(公告)日：2005-04-19

    申请号：US09832685

    申请日：2001-04-10

    申请人： Srinivas Reddy ,  Richard G. Cliff

    发明人： Srinivas Reddy ,  Richard G. Cliff

    IPC分类号： H03K19/177 ,  G06F7/38

    CPC分类号： H03K19/17752 ,  H03K19/17728 ,  H03K19/17736

    摘要： A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be coupled to the programmable interconnect, where they may be coupled with other logic elements of the programmable logic device. Using these tristate structures, the signal pathways of the architecture may be dynamically reconfigured.

    摘要翻译： 包括三态结构的可编程逻辑器件架构。 可编程逻辑器件架构提供了可逻辑地或可编程地控制的三态结构，或两者。 通过这些三态结构，逻辑元件可以耦合到可编程互连，其中它们可以与可编程逻辑器件的其它逻辑元件耦合。 使用这些三态结构，可以动态地重新配置架构的信号路径。

    Programmable logic device with hierarchical interconnection resources
    97.
    发明授权
    Programmable logic device with hierarchical interconnection resources 有权
    具有分层互连资源的可编程逻辑器件

    公开(公告)号：US06417694B1

    公开(公告)日：2002-07-09

    申请号：US09956748

    申请日：2001-09-19

    申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

    摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

    Redundancy circuitry for logic circuits
    99.
    发明授权
    Redundancy circuitry for logic circuits 失效

    公开(公告)号：US6034536A

    公开(公告)日：2000-03-07

    申请号：US982297

    申请日：1997-12-01

    申请人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

    发明人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

    IPC分类号： G06F11/20 ,  G11C29/00 ,  H03K19/177 ,  H03K19/003 ,  H03K19/173

    CPC分类号： H03K19/17764 ,  G11C29/808 ,  H03K19/17728 ,  H03K19/17736

    摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.

    System for distributing clocks using a delay lock loop in a programmable logic circuit
    100.
    发明授权
    System for distributing clocks using a delay lock loop in a programmable logic circuit 失效
    用于在可编程逻辑电路中使用延迟锁定环路分配时钟的系统

    公开(公告)号：US5963069A

    公开(公告)日：1999-10-05

    申请号：US971315

    申请日：1997-11-17

    申请人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    发明人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    IPC分类号： G06F1/10 ,  H03K19/177 ,  H03L7/081 ,  H03L7/087 ,  H03L7/08

    CPC分类号： H03K19/1774 ,  G06F1/10 ,  H03K19/17732 ,  H03L7/0814 ,  H03L7/087

    摘要： A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

    摘要翻译： 一种用于将时钟信号分配给集成电路上的许多点的系统（100）。 该系统包括使用具有特定数字电路的延迟锁定环来完成相位误差检测和延迟元件选择。 在一个实施例中，使用两个触发器来检测相位误差。 在另一个实施例中，使用宏（202）和微相位检测器（218），并且通过使用第一级中的移位寄存器（210）和在第二级中的计数器（220），两级执行延迟元件选择 。 本发明的另一个特征是将参考时钟或同步时钟分配到集成电路上的电路的不同部分的能力。 提供可选择的多个时钟分配系统。