公开(公告)号：US20110260213A1

公开(公告)日：2011-10-27

申请号：US12764329

申请日：2010-04-21

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements. The at least one monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延掺杂的上层 半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的至少一层掺杂剂单层。 所述至少一个掺杂剂单层与源极延伸区域或漏极延伸区域的边缘直接接触。

公开(公告)号：US20110111584A1

公开(公告)日：2011-05-12

申请号：US13005894

申请日：2011-01-13

申请人： Xiangdong Chen ,  Shang-Bin Ko ,  Dae-Gyu Park

发明人： Xiangdong Chen ,  Shang-Bin Ko ,  Dae-Gyu Park

IPC分类号： H01L21/28

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.

摘要翻译： 平面通栅NFET被设计成具有与平面下拉NFET相同的宽度。 为了优化平面下拉NFET和邻接的平面通过栅极NFET之间的β比率，通过向平面通过栅极NFET提供不同的高k金属栅极堆叠来增加平面栅极NFET的阈值电压，而不是 平面下拉NFET。 特别地，形成在高k电介质层上的阈值电压调节电介质层保留在平面通过栅极NFET中，并在平面下拉式NFET中去除。 用于平面通过栅极NFET和平面下拉NFET的组合NFET有源区域基本上是矩形的，这使得能够通过光刻装置对组合的NFET有源区域的图像进行高保真打印。

公开(公告)号：US07872303B2

公开(公告)日：2011-01-18

申请号：US12191425

申请日：2008-08-14

申请人： Kevin K. Chan ,  Qiqing Christine Ouyang ,  Dae-Gyu Park ,  Xinhui Wang

发明人： Kevin K. Chan ,  Qiqing Christine Ouyang ,  Dae-Gyu Park ,  Xinhui Wang

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7848

摘要： At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.

摘要翻译： 在至少一个半导体鳍片的至少一个沟道区域上形成至少一个栅极电介质，栅电极和栅极帽电介质。 在栅电极的侧壁上形成栅极间隔物，在栅电极的两侧露出翅片的端部。 半导体鳍片的暴露部分被垂直和横向蚀刻，从而减小端部中的至少一个半导体翅片的高度和宽度。 绝缘体层的露出部分也可以凹进。 晶格不匹配的半导体材料通过选择性外延生长在至少一个半导体鳍片的剩余端部上，并与外部对准至少一个半导体鳍片。 晶格不匹配材料沿着形成在至少一个半导体鳍片上的finFET的沟道施加纵向应力。

公开(公告)号：US07683418B2

公开(公告)日：2010-03-23

申请号：US12277539

申请日：2008-11-25

申请人： Dae-Gyu Park ,  Oleg G. Gluschenkov ,  Michael A. Gribelyuk ,  Kwong Hon Wong

发明人： Dae-Gyu Park ,  Oleg G. Gluschenkov ,  Michael A. Gribelyuk ,  Kwong Hon Wong

IPC分类号： H01L27/108

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.

摘要翻译： 本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

公开(公告)号：US20100055442A1

公开(公告)日：2010-03-04

申请号：US12203338

申请日：2008-09-03

申请人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

发明人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

IPC分类号： C23C16/513 ,  B32B3/26

CPC分类号： C23C16/45536 ,  C23C16/36 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/3141 ,  H01L21/3148 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76831 ,  Y10T428/24999

摘要： A method of depositing a SiNxCy liner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiNxCy liner on a surface of a low-k substrate having pores on a surface thereon, in which the low-k substrate is repeatedly exposed to a aminosilane-based precursor and a plasma selected from nitrogen, hydrogen, oxygen, helium, and combinations thereof until a thickness of the liner is obtained, and wherein the liner is prevented from penetrating inside the pores of a surface of the substrate. A porous low thermal conductivity substrate having a SiNxCy liner formed thereon by the method is also disclosed.

摘要翻译： 一种通过等离子体增强原子层沉积（PE-ALD）在多孔低热导率（低k）衬底上沉积SiNxCy衬垫的方法，其包括在具有孔的低k衬底的表面上形成SiN xCy衬垫 其中低k衬底反复暴露于基于氨基硅烷的前体和选自氮，氢，氧，氦及其组合的等离子体，直到获得衬垫的厚度，并且其中衬垫是 防止在基板的表面的孔内渗透。 还公开了通过该方法在其上形成SiN xCy衬垫的多孔低热导率衬底。

公开(公告)号：US20090108372A1

公开(公告)日：2009-04-30

申请号：US11924059

申请日：2007-10-25

申请人： Xiangdong Chen ,  Shang-Bin Ko ,  Dae-Gyu Park

发明人： Xiangdong Chen ,  Shang-Bin Ko ,  Dae-Gyu Park

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.

摘要翻译： 平面通栅NFET被设计成具有与平面下拉NFET相同的宽度。 为了优化平面下拉NFET和邻接的平面通过栅极NFET之间的β比率，通过向平面通过栅极NFET提供不同的高k金属栅极堆叠来增加平面栅极NFET的阈值电压，而不是 平面下拉NFET。 特别地，形成在高k电介质层上的阈值电压调节电介质层保留在平面通过栅极NFET中，并在平面下拉式NFET中去除。 用于平面通过栅极NFET和平面下拉NFET的组合NFET有源区域基本上是矩形的，这使得能够通过光刻装置对组合的NFET有源区域的图像进行高保真打印。

公开(公告)号：US07504696B2

公开(公告)日：2009-03-17

申请号：US11306748

申请日：2006-01-10

申请人： Huilong Zhu ,  Zhijiong Luo ,  Dae-Gyu Park

发明人： Huilong Zhu ,  Zhijiong Luo ,  Dae-Gyu Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823878

摘要： Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that is complementary to a second transistor that includes the second gate, wherein the first gate and the second gate are situated on the same substrate. Furthermore, the first metal produces a first threshold voltage characteristic, wherein the first metal comprises tantalum. The second metal produces a second threshold voltage characteristic that differs from the first threshold voltage characteristic, wherein the second metal comprises tungsten.

摘要翻译： 本文的实施例提供了制造具有双金属栅极的CMOS的结构和方法。 具体地，CMOS包括包括第一金属的第一栅极和包括第二金属的第二栅极。 第一栅极包括与包括第二栅极的第二晶体管互补的第一晶体管的一部分，其中第一栅极和第二栅极位于相同的衬底上。 此外，第一金属产生第一阈值电压特性，其中第一金属包括钽。 第二金属产生与第一阈值电压特性不同的第二阈值电压特性，其中第二金属包括钨。

公开(公告)号：US07439128B2

公开(公告)日：2008-10-21

申请号：US11124324

申请日：2005-05-06

申请人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Dae-Gyu Park

发明人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Dae-Gyu Park

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864

摘要： The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.

摘要翻译： 本发明包括一种方法，包括提供基底的步骤; 在基板中形成沟槽; 在沟槽周围形成衬底; 在沟槽内沉积介电层; 然后在电介质层的顶部沉积P型金属，其中电介质层位于P型金属和掩埋板之间。 本发明的另一方面提供一种沟槽电容器，其中所述沟槽电容器包括形成在衬底中的沟槽，在衬底周围形成的掩埋板围绕沟槽; 节点电介质; 以及沉积在沟槽内的P型金属衬垫，其中P型金属衬垫通过节点电介质与掩埋板分离。 P型金属被定义为具有接近于Si价带的功函数的金属，大约等于5.1eV。

公开(公告)号：US20070278590A1

公开(公告)日：2007-12-06

申请号：US11306748

申请日：2006-01-10

申请人： Huilong Zhu ,  Zhijiong Luo ,  Dae-Gyu Park

发明人： Huilong Zhu ,  Zhijiong Luo ,  Dae-Gyu Park

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823878

摘要： Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that is complementary to a second transistor that includes the second gate, wherein the first gate and the second gate are situated on the same substrate. Furthermore, the first metal produces a first threshold voltage characteristic, wherein the first metal comprises tantalum. The second metal produces a second threshold voltage characteristic that differs from the first threshold voltage characteristic, wherein the second metal comprises tungsten.

摘要翻译： 本文的实施例提供了制造具有双金属栅极的CMOS的结构和方法。 具体地，CMOS包括包括第一金属的第一栅极和包括第二金属的第二栅极。 第一栅极包括与包括第二栅极的第二晶体管互补的第一晶体管的一部分，其中第一栅极和第二栅极位于相同的衬底上。 此外，第一金属产生第一阈值电压特性，其中第一金属包括钽。 第二金属产生与第一阈值电压特性不同的第二阈值电压特性，其中第二金属包括钨。

公开(公告)号：US20070262348A1

公开(公告)日：2007-11-15

申请号：US11782351

申请日：2007-07-24

申请人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

发明人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

IPC分类号： H01L21/3205 ,  H01L29/73

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.

摘要翻译： 本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。