公开(公告)号：US06674676B1

公开(公告)日：2004-01-06

申请号：US10444226

申请日：2003-05-23

申请人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

发明人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

IPC分类号： G11C700

CPC分类号： G11C29/846 ,  G11C2207/104

摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.

摘要翻译： 一种列冗余系统，包括用于执行各个微单元内的列元素的冗余交换操作的列冗余设备。 列冗余装置还包括熔丝信息存储装置，第一存储体地址解码机构对与读取操作相关的第一微小区对应的读存储体地址进行解码，第二存储体地址解码机构对与 访问用于写操作的第二微小区。 如果存在包含在第一微单元内的至少一个有缺陷的列元素，则列冗余设备生成与第一微单元中的至少一个缺陷列元素对应的内部列地址。 类似地，如果在第二微小区内包含至少一个有缺陷的列元素，则列冗余设备产生对应于第二微小区中的至少一个缺陷列元素的内部列地址。

公开(公告)号：US06477630B2

公开(公告)日：2002-11-05

申请号：US09257146

申请日：1999-02-24

申请人： Brian Ji ,  Toshiaki Kirihata ,  Dmitry Netis

发明人： Brian Ji ,  Toshiaki Kirihata ,  Dmitry Netis

IPC分类号： G06F1300

CPC分类号： G11C11/4097 ,  G11C11/4087

摘要： A memory structure comprises a plurality of banks (each of the banks including a plurality of blocks) a plurality of timing critical address lines connected to all of the blocks in respective ones of the banks (a number of the critical address lines being equal to a number of the banks), and a plurality of dedicated address lines connected to respective ones of the blocks.

摘要翻译： 存储器结构包括多个存储体（每个存储体包括多个块）连接到相应存储体中的所有块的多个时序关键地址线（关键地址线的数量等于 银行数量）以及连接到各个块的多个专用地址线。

公开(公告)号：US06404264B2

公开(公告)日：2002-06-11

申请号：US09455118

申请日：1999-12-06

申请人： Gabriel Daniel ,  Toshiaki Kirihata

发明人： Gabriel Daniel ,  Toshiaki Kirihata

IPC分类号： H03K1762

CPC分类号： G11C29/83 ,  G11C8/08 ,  G11C17/18

摘要： A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit. Further, current consumption of a fuse latch circuit of the present invention is reduced by adopting NMOS transistors to which a lower voltage level may be applied.

摘要翻译： 根据本发明的用于存储器电路的熔丝锁存器包括多个地址线，从熔丝提供的控制信号线，多路复用器，用于响应于控制信号多路复用多个地址线，其中多路复用器仅具有一种类型 晶体管和用于从多路复用器接收多路复用信号的解码器。 由于多路复用器具有比常规CMOS多路复用器更小的尺寸，因此本发明的熔丝锁存电路具有比常规熔丝锁存器更小的尺寸。 多路复用器优选地仅具有NMOS晶体管。 为了克服由于NMOS阈值电压引起的电压降，本发明使用低阈值NMOS和/或升压多路复用器中的晶体管。 或者，通过使用动态逻辑电路将电压降成功地转换成CMOS电平。 此外，通过采用可施加较低电压电平的NMOS晶体管来减少本发明的熔丝锁存电路的电流消耗。

公开(公告)号：US06326800B1

公开(公告)日：2001-12-04

申请号：US09329895

申请日：1999-06-10

申请人： Toshiaki Kirihata

发明人： Toshiaki Kirihata

IPC分类号： G01R3102

CPC分类号： G01R31/287 ,  G01R31/2879

摘要： A method and apparatus for providing a self-adjusting burn-in test to a device-under-test by dynamically regulating critical burn-in test parameters, such as the supply voltage, and modifying the test conditions, avoiding in the process over and under burn-in. More specifically, the method includes setting an initial set of burn-in operating test conditions and repeatedly adjusting the burn-in operating test conditions while performing the burn-in test until a predetermined reliability target is achieved. The apparatus being described includes a test target, a tester, a reliability analyzer, and a burn-in controller. With this system, the number of fails are measured during burn-in, and the final number of fails after completion of the burn-in test is extrapolated. If the number of fails exceeds a stated reliability objective, the burn-in conditions specified by burn-in controller are reduced, thereby avoiding over burn-in or in the alternative under-burn.

摘要翻译： 一种用于通过动态调节关键老化测试参数（如电源电压）和修改测试条件来为待测器件提供自调整老化测试的方法和设备，避免在过程中和在以下过程 老化 更具体地，该方法包括设置初始的老化操作测试条件集合并且在执行老化测试期间重复地调整老化操作测试条件，直到达到预定的可靠性目标。 所描述的装置包括测试目标，测试器，可靠性分析器和老化控制器。 使用该系统，在老化期间测量故障次数，并且推断完成老化测试后的最终失败次数。 如果故障次数超过规定的可靠性目标，则老化控制器指定的老化条件减少，从而避免过度烧伤或替代烧伤。

公开(公告)号：US06266272B1

公开(公告)日：2001-07-24

申请号：US09364841

申请日：1999-07-30

申请人： Toshiaki Kirihata ,  Daniel Storaska ,  Chandrasekhar Narayan ,  William Tonti ,  Claude Bertin ,  Nick van Heel

发明人： Toshiaki Kirihata ,  Daniel Storaska ,  Chandrasekhar Narayan ,  William Tonti ,  Claude Bertin ,  Nick van Heel

IPC分类号： G11C1450

CPC分类号： G11C16/02 ,  G11C11/005

摘要： A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.

摘要翻译： 部分非易失性动态随机存取存储器（PNDRAM）使用由多个单晶体管（1T）单元或两个晶体管（2T）单元形成的DRAM阵列。 电池可电可编程为非易失性存储器。 这导致具有动态随机存取存储器（DRAM）和电可编程只读存储器（EPROM）的单芯片设计。 集成在PNDRAM中的DRAM和EPROM可以随时重新配置，无论是在制造还是在现场。 PNDRAM具有多个应用，例如将主内存与ID，BIOS或操作系统信息组合在一个芯片中。

公开(公告)号：US6081021A

公开(公告)日：2000-06-27

申请号：US7889

申请日：1998-01-15

申请人： Jeffrey P. Gambino ,  Chandrasekhar Narayan ,  Toshiaki Kirihata

发明人： Jeffrey P. Gambino ,  Chandrasekhar Narayan ,  Toshiaki Kirihata

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L29/00

CPC分类号： H01L28/40 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/5252 ,  H01L28/60 ,  H01L21/31612 ,  H01L21/3185 ,  H01L2924/0002

摘要： An integrated circuit device including a conductor-insulator-conductor structure and a method of manufacturing the structure simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings extend through a second interlevel dielectric to the first interconnect layer. An insulator is deposited in the openings. A trench is then etched into the upper portion of the openings that will become vias while simultaneously removing the insulator from the bottom of the openings that will become vias. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

摘要翻译： 一种包括导体 - 绝缘体 - 导体结构的集成电路器件以及同时形成双重镶嵌通孔同时制造该结构的方法。 第一互连层形成在第一层间电介质上。 开口延伸穿过第二层间介质到第一互连层。 绝缘体沉积在开口中。 然后将沟槽蚀刻到将成为通孔的开口的上部中，同时从将成为通孔的开口的底部移除绝缘体。 然后将导体沉积在开口中并在沟槽中，并使用化学机械抛光（CMP）来对导体进行图案化。 然后沉积第三层间电介质，形成延伸到导体的开口，并且沉积和图案化第三互连层导体。

公开(公告)号：US5940335A

公开(公告)日：1999-08-17

申请号：US122426

申请日：1998-07-24

申请人： Toshiaki Kirihata

发明人： Toshiaki Kirihata

IPC分类号： G11C29/04 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/804 ,  G11C29/808

摘要： A variable size redundancy replacement (VSRR) arrangement for making a memory fault-tolerant. A redundancy array supporting the memory includes a plurality of variable size redundancy units, each of which encompasses a plurality of redundancy elements. The redundancy units, used for repairing faults in the memory, are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This configuration significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.

摘要翻译： 用于使存储器容错的可变大小冗余替换（VSRR）布置。 支持存储器的冗余阵列包括多个可变大小的冗余单元，每个冗余单元包括多个冗余元件。 用于修复存储器故障的冗余单元是独立控制的。 维修单元内的所有冗余元件优选同时更换。 冗余单元中的冗余元件通过解码地址线来控制。 表征此配置的可变大小使得可以选择最有效的冗余单元，特别是最接近要替换的故障群集大小的冗余单元。 这种配置可显着降低由添加的冗余元件和控制电路产生的开销，同时提高访问速度并降低功耗。 最后，由优先级解码器控制的容错块冗余使得可以使用VSRR单元来修复块冗余中的故障，在其用于替换存储器内的有缺陷块之前。

公开(公告)号：US5848008A

公开(公告)日：1998-12-08

申请号：US937528

申请日：1997-09-25

申请人： Toshiaki Kirihata ,  Hing Wong ,  Bozidar Krsnik

发明人： Toshiaki Kirihata ,  Hing Wong ,  Bozidar Krsnik

IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C29/04 ,  G11C29/50 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C29/50

摘要： A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.

摘要翻译： 提供一种使用数字可控位线均衡器产生浮动位线测试模式的方法。 该方法利用数字控制的虚拟定时周期来检测浮动位线测试模式期间的泄漏位线。 产生负脉冲+ E，ovs TEST + EE信号，使位线均衡器变为低电平，并导致浮置位线状态。 虚拟定时周期的实现消除了在位线测试模式期间对内部定时的额外外部控制的需要。 在虚拟定时周期结束时，正常读取操作继续而不中断。

公开(公告)号：US5764655A

公开(公告)日：1998-06-09

申请号：US887374

申请日：1997-07-02

申请人： Toshiaki Kirihata ,  Christopher D. Wait

发明人： Toshiaki Kirihata ,  Christopher D. Wait

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/273 ,  G11C29/12 ,  H01L21/66 ,  G06F11/00

CPC分类号： G06F11/2635 ,  G01R31/318505 ,  G01R31/31702

摘要： An integrated circuit chip and an electronic system are disclosed, each incorporating a self-test system. The integrated circuit chip includes capability for Built In Self Test (BIST) and a non-volatile memory where the BIST may be self-programmable. The electronic system comprises, an integrated circuit chip which includes on the chip Built In Self Test (BIST) and a non-volatile memory, together with an off-chip test target. The integrated circuit chip and the electronic system are particularly useful for simplifying the testing of electronic products both in manufacturing and in the field, and are even more particularly useful in eliminating the need for large, complex, high speed testers in the manufacturing environment, substituting instead a simple power chuck to plug the product into.

摘要翻译： 公开了一种集成电路芯片和电子系统，其中包括自检系统。 集成电路芯片包括内置自检（BIST）和非易失性存储器，其中BIST可以是自编程的。 电子系统包括集成电路芯片，其包括芯片内置自测（BIST）和非易失性存储器，以及片外测试目标。 集成电路芯片和电子系统对于简化制造和现场的电子产品的测试特别有用，并且甚至更具体地用于消除在制造环境中对大型，复杂的高速测试仪的需要，代替 而是一个简单的动力卡盘来插入产品。

公开(公告)号：US5615164A

公开(公告)日：1997-03-25

申请号：US477063

申请日：1995-06-07

申请人： Toshiaki Kirihata ,  Hing Wong

发明人： Toshiaki Kirihata ,  Hing Wong

IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/02 ,  G11C29/06 ,  G11C29/12 ,  G11C29/34 ,  G11C29/50 ,  G11C8/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/34 ,  G11C29/50 ,  G11C8/10 ,  G11C11/401

摘要： A latched row decoder for a Random Access Memory (RAM). The Decoder includes a set-reset latch that is set when addressed and remains set until reset by a PRE signal; address select logic; a reset device; and gated word line drives. The latch, when set, enables four word line drivers that are driven individually depending on two row address bits. During test, latched decoders may be selected sequentially and not reset, leaving drivers enabled until a test is complete. Thus some or all word lines may be driven simultaneously during test. A RAM including the latched decoder of the present invention has a normal random access mode and at least 4 test modes. The test modes are: Long t.sub.RAS word line disturb mode; toggled word line disturb mode; transfer gate stress mode; and a stress test mode.

摘要翻译： 用于随机存取存储器（RAM）的锁存行解码器。 解码器包括设置复位锁存器，其在寻址时被置位并保持置位，直到由PRE信号复位; 地址选择逻辑; 复位装置; 和门控驱动器。 当锁存器置位时，可以根据两个行地址位单独驱动四个字线驱动器。 在测试期间，锁存解码器可以顺序选择并且不复位，使驱动器启用，直到测试完成。 因此，在测试期间可以同时驱动一些或所有字线。 包括本发明的锁存解码器的RAM具有正常的随机存取模式和至少4个测试模式。 测试模式为：长tRAS字线干扰模式; 切换字线干扰模式; 传输门应力模式; 和压力测试模式。