公开(公告)号：US11762552B2

公开(公告)日：2023-09-19

申请号：US17201924

申请日：2021-03-15

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Cristian P. Masgras

IPC: G06F3/06

CPC classification number: G06F3/0601 ,  G06F3/0604 ,  G06F3/0673

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

公开(公告)号：US11637235B2

公开(公告)日：2023-04-25

申请号：US16744963

申请日：2020-01-16

Applicant: Everspin Technologies, Inc.

Inventor： Sumio Ikegawa ,  Han Kyu Lee ,  Sanjeev Aggarwal ,  Jijun Sun ,  Syed M. Alam ,  Thomas Andre

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14 ,  H01L27/22

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

公开(公告)号：US10923170B2

公开(公告)日：2021-02-16

申请号：US16358414

申请日：2019-03-19

Applicant: Everspin Technologies, Inc.

Inventor： Jason Janesky ,  Syed M. Alam ,  Dimitri Houssameddine ,  Mark Deherrera

IPC: G11C11/16 ,  G11C29/12 ,  G11C29/02 ,  G11C29/50 ,  G11C17/16

Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

公开(公告)号：US10650899B2

公开(公告)日：2020-05-12

申请号：US15499136

申请日：2017-04-27

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam

IPC: G11C16/22 ,  G11C11/4076 ,  G11C29/52 ,  G11C11/4078 ,  G06F12/02

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed. Calibration and testing sequences are also supported in which a non-destructive mode preserves data stored in a non-volatile memory array and status bits used to indicate open pages are cleared so later inadvertent delayed write-back operations as a result of the calibration or testing do not corrupt the non-volatile data.

公开(公告)号：US10199122B2

公开(公告)日：2019-02-05

申请号：US15852678

申请日：2017-12-22

Applicant: Everspin Technologies Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G06F7/02 ,  H03M13/00 ,  G11C29/50 ,  G11C11/16 ,  G06F11/08 ,  G06F11/10 ,  G11C29/04

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US10020041B1

公开(公告)日：2018-07-10

申请号：US15602856

申请日：2017-05-23

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Chitra K. Subramanian

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1675 ,  G11C27/024

Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.

公开(公告)号：US09740431B2

公开(公告)日：2017-08-22

申请号：US15212271

申请日：2016-07-17

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Dietmar Gogl

IPC: G11C11/00 ,  G06F3/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C8/04 ,  G06F12/02 ,  G06F12/06 ,  G11C11/16 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/00 ,  G06F13/16 ,  G11C11/4091

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C7/1042 ,  G11C7/1072 ,  G11C8/04 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/0036

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

公开(公告)号：US09679627B2

公开(公告)日：2017-06-13

申请号：US14502367

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Dimitri Houssameddine ,  Syed M. Alam ,  Jon Slaughter ,  Chitra Subramanian

IPC: G11C16/04 ,  G11C11/16 ,  G06F12/0804

CPC classification number: G11C11/1675 ,  G06F12/0804 ,  G11C11/1677 ,  Y02D10/13

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US20170092347A1

公开(公告)日：2017-03-30

申请号：US15369246

申请日：2016-12-05

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0069 ,  G11C2213/79

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

公开(公告)号：US09583169B2

公开(公告)日：2017-02-28

申请号：US15149401

申请日：2016-05-09

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre ,  Halbert S. Lin

IPC: G11C11/00 ,  G11C11/16 ,  G11C8/08

CPC classification number: G11C11/1673 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1693 ,  G11C11/1697

Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

Abstract translation: 升压的电源电压发生器被选择性地激活和去激活，以允许以稳定的升压电压来执行对升压电压的变化敏感的操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。 这样的技术包括当停用时存储对应于电压发生器的状态信息，其中在重新激活电压发生器时使用存储的状态信息。 存储状态信息可以包括提供给电压发生器的时钟信号的状态。