公开(公告)号：US09418899B1

公开(公告)日：2016-08-16

申请号：US14611769

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping Shen ,  Min-hwa Chi ,  Xusheng Wu ,  Weihua Tong ,  Haiting Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/3215 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28568 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract translation: 提供一种形成用于nFET和pFET的RMG多WF层的方法，以及所得到的器件。 实施例包括形成Si翅片; 形成nFET RMG沟槽和pFET RMG沟槽; 在nFET和pFET RMG沟槽中形成第一Ti层; 在pFET RMG沟槽中以0°注入角垂直注入第一Ti层中的N 2; 对N 2注入的第一Ti层退火以在pFET RMG沟槽中形成TiN层; 剥离第一Ti层的未反应的Ti; 在nFET和pFET RMG沟槽中形成第二Ti层; 在0°垂直放置第二Ti层中的Al或C; 退火Al或C注入的第二Ti层，分别在nFET和pFET RMG沟槽的底部形成TiAl或TiC; 并用Al或W填充nFET和pFET RMG沟槽。

公开(公告)号：US09396995B1

公开(公告)日：2016-07-19

申请号：US14634080

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Min-hwa Chi ,  Garo Derderian ,  Wen-Pin Peng

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/263 ,  H01L21/3065 ,  H01L21/265 ,  H01L29/49

CPC classification number: H01L21/7684 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/456

Abstract: A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON layer on side surfaces of the TT; performing a GCIB vertical etching at a 0° angle; implanting Si into the TT by an angled PAI; removing a portion of the TT by Ar sputtering and a remote plasma assisted dry etch process; forming NiSi on the S/D region at the bottom of the TT; and filling the TT with contact metal over the NiSi.

Abstract translation: 提供了一种在MOL中形成金属化接触的方法。 实施例包括通过ILD形成TT到S / D区域; 在TT的侧表面上形成SiOC，SiCN或SiON层; 以0°角执行GCIB垂直蚀刻; 通过角度PAI将Si注入TT; 通过Ar溅射和远程等离子体辅助干蚀刻工艺去除TT的一部分; 在TT底部的S / D区域形成NiSi; 并用NiSi上的接触金属填充TT。

公开(公告)号：US09379186B1

公开(公告)日：2016-06-28

申请号：US14610140

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qin Wang ,  Min-hwa Chi ,  Meixiong Zhao ,  Zhaoxu Shen ,  Haiting Wang ,  Lucas M. Salazar ,  Lan Yang

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/4236 ,  H01L21/823412 ,  H01L21/823456 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628

Abstract: Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate between the spacers to form inner or outer sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench.

Abstract translation: 公开了制备具有更长有效栅极长度的CMOS晶体管的方法和所得到的器件。 实施例包括在基板上在其相对侧上形成由间隔物结合的虚拟栅极; 去除伪栅极以在间隔物之间​​形成沟槽; 修改间隔件之间的衬底的栅极通道部分以形成内侧壁或外侧壁; 在修改的栅极沟道部分上沉积保形高k电介质层; 并在沟槽中形成金属栅极。

公开(公告)号：US20160104541A1

公开(公告)日：2016-04-14

申请号：US14514289

申请日：2014-10-14

Applicant: GlobalFoundries Inc.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  G11C17/18

CPC classification number: G11C17/12 ,  G11C17/18 ,  H01L27/11233

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract translation: 所公开的至少一种方法，装置和系统涉及将数据硬编码到集成电路装置中。 提供集成电路装置。 接收到集成电路装置的一部分的硬布线信息的数据。 应力电压信号被提供给集成电路器件的晶体管的一部分，用于引起晶体管部分的电介质击穿以硬接线数据。

公开(公告)号：US09252272B2

公开(公告)日：2016-02-02

申请号：US14083164

申请日：2013-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin.

Abstract translation: 这里在一个实施例中阐述了具有从体硅衬底延伸的翅片的FinFET半导体器件，其中形成为围绕鳍的一部分围绕栅极缠绕，并且其中靠近与栅极对准的鳍的沟道区域 形成与栅极对准的局部掩埋氧化物区域。 在一个实施例中，局部掩埋氧化物区域形成在鳍片的沟道区域的下方。

公开(公告)号：US09023705B1

公开(公告)日：2015-05-05

申请号：US14069868

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abhijeet Paul ,  Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8232 ,  H01L29/423 ,  H01L27/088 ,  H01L27/105 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/8232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 所述方法包括在形成在衬底鳍上方的空腔中形成不同半导体材料的这种交替层，然后使用栅极第一或栅极末端技术在鳍周围形成栅极结构。

公开(公告)号：US20140134814A1

公开(公告)日：2014-05-15

申请号：US13674142

申请日：2012-11-12

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Hoong Shing Wong ,  Min-hwa Chi

IPC: H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/823431 ,  H01L21/823821

Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure. An un-merged source/drain region is formed in the void and a merged source/drain region is formed on the un-etched fin structure.

Abstract translation: 公开了具有外延形成的源极和漏极区域的FinFET结构的半导体集成电路的制造方法。 例如，制造集成电路的方法包括在半导体衬底上形成多个硅鳍结构，在翅片结构的垂直侧壁上形成一次性间隔物，并在氧化硅材料上方并在一次性衬垫上方沉积氧化硅材料。 该方法还包括在至少一个翅片结构的侧壁上各向异性地蚀刻翅片结构和一次性间隔物中的至少一个，从而在氧化硅材料中留下空隙，并从中将氧化硅材料和一次性间隔件从 至少另一个翅片结构，同时留下至少一个其它鳍状结构未蚀刻。 此外，该方法包括在空隙中和未蚀刻的鳍结构上外延生长硅材料。 在空隙中形成未合并的源极/漏极区，并且在未蚀刻的鳍结构上形成合并的源极/漏极区。

公开(公告)号：US10756213B2

公开(公告)日：2020-08-25

申请号：US16433626

申请日：2019-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/10 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

公开(公告)号：US10388790B2

公开(公告)日：2019-08-20

申请号：US15082103

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/10

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

公开(公告)号：US10177157B2

公开(公告)日：2019-01-08

申请号：US15792527

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L27/11 ,  H01L21/82 ,  H01L27/092 ,  H01L21/8238

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.