公开(公告)号：US08816391B2

公开(公告)日：2014-08-26

申请号：US12615996

申请日：2009-11-10

申请人： Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L29/772

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7848

摘要： An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof.

摘要翻译： 集成电路结构包括衬底和衬底上的沟道。 该通道包括由III族和V族元素形成的第一III-V族化合物半导体材料。 门结构在通道之上。 源极/漏极区域与沟道相邻并且包括由掺杂的基团IV半导体材料形成的IV族区域，该掺杂基团IV半导体材料主要由硅，锗及其组合组成。

公开(公告)号：US08815712B2

公开(公告)日：2014-08-26

申请号：US13414357

申请日：2012-03-07

申请人： Cheng-Tien Wan ,  You-Ru Lin ,  Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Tien Wan ,  You-Ru Lin ,  Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/36 ,  H01L21/20

CPC分类号： H01L21/3065 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02658 ,  H01L29/66636 ,  H01L29/78

摘要： A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.

摘要翻译： 在第一半导体区域的表面上进行处理，其中使用包括含氧气体和用于蚀刻半导体材料的蚀刻气体的处理气体进行处理。 进行外延以在第一半导体区域的表面上生长第二半导体区域。

公开(公告)号：US08759203B2

公开(公告)日：2014-06-24

申请号：US12842221

申请日：2010-07-23

申请人： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

发明人： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC分类号： H01L21/20

CPC分类号： H01L21/02647 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02617 ,  H01L21/02639

摘要： A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.

摘要翻译： 形成集成电路结构的方法包括在衬底的至少一部分上形成绝缘层; 在所述绝缘层的顶表面上形成多个半导体柱。 多个半导体柱由绝缘层的一部分水平隔开。 以周期性图案分配多个半导体柱。 该方法还包括从半导体柱的顶表面和侧壁外延生长III-V族化合物半导体膜。

公开(公告)号：US08726220B2

公开(公告)日：2014-05-13

申请号：US13416742

申请日：2012-03-09

申请人： Yi-Tang Lin ,  Cheok-Kei Lei ,  Shu-Yu Chen ,  Yu-Ning Chang ,  Hsiao-Hui Chen ,  Chih-Sheng Chang ,  Chien-Wen Chen ,  Clement Hsingjen Wann

发明人： Yi-Tang Lin ,  Cheok-Kei Lei ,  Shu-Yu Chen ,  Yu-Ning Chang ,  Hsiao-Hui Chen ,  Chih-Sheng Chang ,  Chien-Wen Chen ,  Clement Hsingjen Wann

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5068 ,  H01L21/823821 ,  H01L27/0207

摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 分析平面布局，并以相符的方式生成对应的FinFET结构。 然后优化所得的FinFET结构。 在验证并输出FinFET布局之前，可能会产生虚拟图案和新的金属层。

公开(公告)号：US08629040B2

公开(公告)日：2014-01-14

申请号：US13298112

申请日：2011-11-16

申请人： Kai-Tai Chang ,  Yi-Shan Chen ,  Hsin-Chih Chen ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Kai-Tai Chang ,  Yi-Shan Chen ,  Hsin-Chih Chen ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/76

CPC分类号： H01L21/02653 ,  H01L21/02639 ,  H01L21/0337 ,  H01L21/76224 ,  H01L21/76229

摘要： A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.

摘要翻译： 一种方法包括在衬底上形成硬掩模，图案化硬掩模以形成第一多个沟槽，以及将电介质材料填充到第一多个沟槽中以形成多个电介质区域。 硬掩模从多个电介质区域之间移除，其中第二多个沟槽被去除的硬掩模留下。 进行外延步骤以在第二多个沟槽中生长半导体材料。

公开(公告)号：US08617976B2

公开(公告)日：2013-12-31

申请号：US12616002

申请日：2009-11-10

申请人： Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/3205

CPC分类号： H01L29/78 ,  H01L21/28264 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/66628 ,  H01L29/66863 ,  H01L29/7783 ,  H01L29/8128

摘要： A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer.

公开(公告)号：US20130224952A1

公开(公告)日：2013-08-29

申请号：US13404819

申请日：2012-02-24

申请人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

发明人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

IPC分类号： H01L21/3205 ,  H01L21/683 ,  H01L21/687 ,  H01L21/31

CPC分类号： H01L21/687 ,  H01L21/6838 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

摘要： An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.

摘要翻译： 提供了一种形成半导体结构的装置和方法。 该装置包括：基板保持件，其保持基板，使得处理表面是弯曲的，例如凸形或凹形。 基板使用点接触保持就位，多个连续接触部分围绕基板延伸，和/或完全围绕基板延伸的连续环。 处理可以包括例如形成源极/漏极区域，沟道区域，硅化物，应力存储层等。

公开(公告)号：US20130171792A1

公开(公告)日：2013-07-04

申请号：US13414357

申请日：2012-03-07

申请人： Cheng-Tien Wan ,  You-Ru Lin ,  Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Tien Wan ,  You-Ru Lin ,  Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/762 ,  H01L21/336

CPC分类号： H01L21/3065 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02658 ,  H01L29/66636 ,  H01L29/78

摘要： A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.

摘要翻译： 在第一半导体区域的表面上进行处理，其中使用包括含氧气体和用于蚀刻半导体材料的蚀刻气体的处理气体进行处理。 进行外延以在第一半导体区域的表面上生长第二半导体区域。

公开(公告)号：US08455929B2

公开(公告)日：2013-06-04

申请号：US12827709

申请日：2010-06-30

申请人： Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L27/085

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A device includes a semiconductor substrate, and insulation regions in the semiconductor substrate. Opposite sidewalls of the insulation regions have a spacing between about 70 nm and about 300 nm. A III-V compound semiconductor region is formed between the opposite sidewalls of the insulation regions.

摘要翻译： 一种器件包括半导体衬底和半导体衬底中的绝缘区域。 绝缘区域的相对侧壁的间隔为约70nm至约300nm。 在绝缘区域的相对侧壁之间形成III-V族化合物半导体区域。

公开(公告)号：US20130011984A1

公开(公告)日：2013-01-10

申请号：US13178330

申请日：2011-07-07

申请人： Kang-Wei Wang ,  Clement Hsingjen Wann ,  Chih-Hsin Ko

发明人： Kang-Wei Wang ,  Clement Hsingjen Wann ,  Chih-Hsin Ko

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7848

摘要： A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain region, wherein the step of epitaxially growing is performed using hexachlorodisilane as a precursor.

摘要翻译： 一种方法包括在半导体区域上形成栅极叠层，并使半导体区域凹陷以形成邻近栅叠层的凹陷。 在凹部中外延生长含硅半导体区域以形成源极/漏极区域，其中使用六氯二硅烷作为前体进行外延生长的步骤。