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    PIN COUNT SOCKET HAVING REDUCED PIN COUNT AND PATTERN TRANSFORMATION
    91.
    发明申请
    PIN COUNT SOCKET HAVING REDUCED PIN COUNT AND PATTERN TRANSFORMATION 审中-公开

    公开(公告)号：US20200296852A1

    公开(公告)日：2020-09-17

    申请号：US16888069

    申请日：2020-05-29

    Applicant: Intel Corporation

    Inventor： Srikant Nekkanty ,  Zhichao Zhang ,  Kemal Aygun

    IPC: H05K7/10 ,  H05K1/11 ,  H05K7/14 ,  H05K1/02

    Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

    Pin count socket having reduced pin count and pattern transformation
    92.
    发明授权
    Pin count socket having reduced pin count and pattern transformation 有权

    公开(公告)号：US10716231B2

    公开(公告)日：2020-07-14

    申请号：US16146908

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Srikant Nekkanty ,  Zhichao Zhang ,  Kemal Aygun

    IPC: H01R12/00 ,  H05K7/10 ,  H05K1/11 ,  H05K7/14 ,  H05K1/02

    Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

    HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE
    94.
    发明申请
    HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE 审中-公开

    公开(公告)号：US20200168553A1

    公开(公告)日：2020-05-28

    申请号：US16774508

    申请日：2020-01-28

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

    Interconnect routing configurations and associated techniques
    96.
    发明授权
    Interconnect routing configurations and associated techniques 有权

    公开(公告)号：US10283453B2

    公开(公告)日：2019-05-07

    申请号：US15297005

    申请日：2016-10-18

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

    IPC: H01L21/768 ,  H01L23/538 ,  G06F17/50 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

    Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

    FINE FEATURE FORMATION TECHNIQUES FOR PRINTED CIRCUIT BOARDS
    97.
    发明申请
    FINE FEATURE FORMATION TECHNIQUES FOR PRINTED CIRCUIT BOARDS 审中-公开

    公开(公告)号：US20190098764A1

    公开(公告)日：2019-03-28

    申请号：US16081487

    申请日：2016-04-02

    Applicant: INTEL CORPORATION

    Inventor： ERIC LI ,  Kemal Aygun ,  Kai Xiao ,  Gong Ouyang ,  Zhichao Zhang

    IPC: H05K3/00 ,  H05K1/02 ,  H05K3/02

    Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fme conductive features on the LDI PCB by performing a fme feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fme gap region 308 within the conductive structure. Other embodiments are described and claimed.

    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION
    99.
    发明申请
    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 审中-公开

    公开(公告)号：US20180315688A1

    公开(公告)日：2018-11-01

    申请号：US16026824

    申请日：2018-07-03

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

    Chip-to-chip interconnect with embedded electro-optical bridge structures
    100.
    发明授权
    Chip-to-chip interconnect with embedded electro-optical bridge structures 有权

    公开(公告)号：US09971089B2

    公开(公告)日：2018-05-15

    申请号：US14964426

    申请日：2015-12-09

    Applicant: Intel Corporation

    Inventor： Zhichao Zhang ,  Kemal Aygun ,  Robert L. Sankman

    IPC: G02B6/12 ,  G02B6/42

    CPC classification number: G02B6/12004 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4295 ,  G02B2006/12121 ,  G02B2006/12142 ,  G02B2006/12147

    Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.

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