METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE
    91.
    发明申请
    METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE 有权
    PCRAT装置中加热器和相变材料之间的均匀接触面积的方法和结构

    公开(公告)号:US20090026432A1

    公开(公告)日:2009-01-29

    申请号:US11781728

    申请日:2007-07-23

    IPC分类号: H01L29/02 H01L21/20

    摘要: A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process.

    摘要翻译: PCRAM(相变随机存取存储器)半导体器件中的PCM(相变存储器)单元包括由加热膜隐藏接触的相变材料。 相变材料形成在具有至少一个向下延伸的凹部的大致平坦的表面的表面上。 相变材料填充凹部并接触形成凹部底部的加热器膜的上边缘。 在初始形成平坦表面之后,使用选择性蚀刻工艺来使用选择性和各向同性蚀刻工艺将加热器膜的顶部边缘退回到平坦表面下方。

    EMBEDDED BONDING PAD FOR BACKSIDE ILLUMINATED IMAGE SENSOR
    92.
    发明申请
    EMBEDDED BONDING PAD FOR BACKSIDE ILLUMINATED IMAGE SENSOR 有权
    用于背面照明图像传感器的嵌入式粘合垫

    公开(公告)号:US20090020842A1

    公开(公告)日:2009-01-22

    申请号:US11778183

    申请日:2007-07-16

    IPC分类号: H01L31/00

    摘要: The present disclosure provide a microelectronic device. The microelectronic device includes a sensing element formed in the semiconductor substrate; a trench isolation feature formed in the semiconductor substrate; a bonding pad formed at least partially in the trench isolation feature; and interconnect features formed over the sensing element and the trench isolation feature, being coupled to the sensing element and the bonding pad, and isolated from each other by interlayer dielectric.

    摘要翻译: 本公开提供了一种微电子器件。 微电子器件包括形成在半导体衬底中的感测元件; 形成在半导体衬底中的沟槽隔离特征; 至少部分地形成在所述沟槽隔离特征中的接合焊盘; 以及形成在感测元件上的互连特征和沟槽隔离特征,耦合到感测元件和接合焊盘,并且通过层间电介质彼此隔离。

    METHODS FOR FABRICATING IMAGE SENSOR DEVICES
    94.
    发明申请
    METHODS FOR FABRICATING IMAGE SENSOR DEVICES 有权
    用于制作图像传感器装置的方法

    公开(公告)号:US20080061330A1

    公开(公告)日:2008-03-13

    申请号:US11531290

    申请日:2006-09-13

    IPC分类号: H01L31/062

    摘要: Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer.

    摘要翻译: 提供了图像传感器装置及其制造方法。 图像传感器装置的示例性实施例包括支撑衬底。 在支撑衬底上形成钝化结构。 在钝化结构上形成互连结构。 第一半导体层形成在互连结构上,具有第一和第二表面,其中第一和第二表面是相对的表面。 至少一个感光装置从其第一表面形成在第一半导体层之上/之中。 滤色器层从其第二表面形成在第一半导体层上。 在滤色器层上形成至少一个微透镜。

    Magnetic memory cells and manufacturing methods
    95.
    发明申请
    Magnetic memory cells and manufacturing methods 有权
    磁记忆体和制造方法

    公开(公告)号:US20070096230A1

    公开(公告)日:2007-05-03

    申请号:US11610760

    申请日:2006-12-14

    IPC分类号: H01L43/00 H01L29/82

    CPC分类号: H01L43/12 H01L27/228

    摘要: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

    摘要翻译: 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层,然后使用平坦化处理去除绝缘层的部分的方法,通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔,例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。

    Process to improve programming of memory cells
    98.
    发明授权
    Process to improve programming of memory cells 有权
    改善存储单元编程的过程

    公开(公告)号:US07153755B2

    公开(公告)日:2006-12-26

    申请号:US11044813

    申请日:2005-01-26

    IPC分类号: H01L21/762

    摘要: A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

    摘要翻译: 提供了一种用于制造半导体衬底的方法,该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离(STI)结构彼此隔离的区域。 该方法包括以下步骤:形成覆盖半导体衬底的表面和STI结构表面的底部抗反射涂层(BARC)层; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分,并且部分地蚀刻所述STI结构中的所述至少一个,以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。 该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

    Etching method for forming a square cornered polysilicon wordline electrode
    100.
    发明申请
    Etching method for forming a square cornered polysilicon wordline electrode 失效
    用于形成正方形多晶硅字线电极的蚀刻方法

    公开(公告)号:US20050079672A1

    公开(公告)日:2005-04-14

    申请号:US10685127

    申请日:2003-10-14

    摘要: A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

    摘要翻译: 一种分裂栅FET字线电极结构及其形成方法,包括改进的多晶硅蚀刻工艺,包括提供包括第一裸露多晶硅部分和相邻氧化物部分的半导体晶片工艺表面; 在所述暴露的多晶硅部分上形成第一氧化物层; 在第一暴露的多晶硅部分和相邻的氧化物部分上覆盖多晶硅层; 在所述多晶硅层上形成硬掩模层; 执行多步反应离子蚀刻(RIE)工艺以蚀刻穿过硬掩模层并蚀刻穿过多晶硅层的厚度部分,以形成与具有向上突出的外部多晶硅栅栏部分的氧化物部分相邻的第二多晶硅部分; 使所述半导体晶片工艺表面与HF水溶液接触; 并且执行下游等离子体蚀刻工艺以去除多晶硅栅栏部分。