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    INTERCONNECT STRUCTURE
    92.
    发明申请
    INTERCONNECT STRUCTURE 有权
    互连结构

    公开(公告)号：US20100264543A1

    公开(公告)日：2010-10-21

    申请号：US12424843

    申请日：2009-04-16

    申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76847 ,  H01L21/76805 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.

    摘要翻译： 公开了用于形成半导体互连结构的互连结构和方法。 在一个实施例中，互连结构包括：衬底，其包括第一衬里层和其上的第一金属层; 在所述第一金属层和所述衬底上的介电阻挡层; 电介质阻挡层上的层间电介质层; 所述通孔在所述层间电介质层，所述电介质阻挡层和所述第一金属层之间延伸，所述通孔在其上包括第二衬垫层和第二金属层; 以及位于所述第二衬垫层和所述第一金属层之间的扩散阻挡层，其中所述扩散阻挡层的一部分位于所述电介质阻挡层下方。

    Structure and method for dual surface orientations for CMOS transistors
    93.
    发明授权
    Structure and method for dual surface orientations for CMOS transistors 失效
    用于CMOS晶体管的双面取向的结构和方法

    公开(公告)号：US07808082B2

    公开(公告)日：2010-10-05

    申请号：US11559571

    申请日：2006-11-14

    申请人： Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    发明人： Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L21/335

    CPC分类号： H01L21/30608 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/823821 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7853

    摘要： The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

    摘要翻译： 本发明提供了提供具有不同于半导体衬底通常提供的不同晶体取向的刻面的结构和方法。 通过掩蔽半导体表面的一部分并将其余部分暴露于比其它晶体学优化蚀刻一组结晶平面的各向异性蚀刻工艺，在半导体衬底上形成具有不同于衬底取向的不同表面取向的新面。 或者，可以利用选择性外延生成新的面。 如此形成的小面被连接以在横截面中形成λ形轮廓。 新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。 在具有接合形成λ形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，避免了在电流方向上的任何拐点。

    Reliable via contact interconnect structure
    94.
    发明授权
    Reliable via contact interconnect structure 有权
    通过接触互连结构可靠

    公开(公告)号：US07800228B2

    公开(公告)日：2010-09-21

    申请号：US11435410

    申请日：2006-05-17

    申请人： Chih-Chao Yang ,  Oscar Van Der Straten

    发明人： Chih-Chao Yang ,  Oscar Van Der Straten

    IPC分类号： H01L23/52

    CPC分类号： H01L21/76834 ,  H01L21/288 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76852 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.

    摘要翻译： 提供了可靠和机械强的互连结构，其不包括开口底部的特别是在通孔底部的气泡特征。 相反，本发明的互连结构利用选择性地沉积在位于较低互连级别的导电特征的暴露表面上的含Co缓冲层。 选择性沉积通过存在于上部互连电平的电介质材料中的至少一个开口进行。 选择性沉积通过电镀或无电镀进行。 含Co缓冲层包含Co和P和B中的至少一个.W可选地也可以存在于含Co缓冲层中。

    Semiconductor wiring structures including dielectric cap within metal cap layer
    96.
    发明授权
    Semiconductor wiring structures including dielectric cap within metal cap layer 有权
    包括金属盖层内的电介质盖的半导体布线结构

    公开(公告)号：US07732924B2

    公开(公告)日：2010-06-08

    申请号：US11761495

    申请日：2007-06-12

    申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： H01L23/52

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76865 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

    摘要翻译： 包括其中具有金属布线的电介质层，从金属布线向下延伸的孔，在金属布线上方的金属盖层和位于金属盖层的一部分内的局部电介质盖的半导体布线结构 公开了与金属布线的接触和相关方法。 局部电介质盖表示在双镶嵌互连的金属布线中有意创造的弱点，其在管线中引起电迁移（EM）空隙，而不是在从金属布线向下延伸的通孔的底部。 由于线路中的临界空隙尺寸失效，特别是金属盖层（衬垫）冗余度，远远大于通孔失效，所以EM寿命可以显着提高。

    High aspect ratio electroplated metal feature and method
    99.
    发明授权
    High aspect ratio electroplated metal feature and method 失效
    高宽比电镀金属特点及方法

    公开(公告)号：US07727890B2

    公开(公告)日：2010-06-01

    申请号：US11953359

    申请日：2007-12-10

    申请人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

    发明人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

    IPC分类号： H01L21/44

    CPC分类号： C25D5/02 ,  Y10T428/24331 ,  Y10T428/24917

    摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

    摘要翻译： 公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料 没有接缝和/或空隙。 此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层 金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。