摘要:
A memory device having a smaller circuit area but efficiently used is provided. A plurality of main word lines (MWL) extending in a row direction are connected through respective bank latches (BL) to a single global word line (GWL) extending across banks (BANK0, BANK1). Selective activation of an enable signal (BLE) and the global word line (GWL) selects one of the bank latches (BL) to selectively activate an associated main word line (MWL). This state is held by the selected bank latch (BL) after the enable signal (BLE) is inactivated. Then, another enable signal (BLE) is activated to selectively activate another main word line (MWL). Sub-decoders (SD) connected to the main word lines (MWL) are selected independently of each other to independently activate word lines (WL) for each bank (BANK).
摘要:
A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.
摘要:
A semiconductor memory having memory cells is formed on a semiconductor substrate. Each of the memory cells has a transistor and a capacitor. The transistor includes a channel region, a drain region and a source region aligned in a line and being insulated by an insulation film from an adjacent cell. Each of the memory cells has a gate electrode formed on the channel region with a gate insulating film therebetween. A pad electrode makes electrical contact with one of the source and drain regions of the memory cell and extends over the insulation film. A bit line makes electrical contact with the pad electrode above, extends in parallel to the line and is laterally isolated from one of the source and drain regions. A first insulating film is formed on the semiconductor substrate over the bit line. A first capacitor electrode is formed on the first insulating film, making electrical contact with the other of the source and drain regions of the memory cell through a contact hole opened through the first insulating film and insulated from the bit line by the first insulating film. A second capacitor electrode is formed on the first capacitor electrode with a second insulating film provided therebetween. The insulation film is embedded in a groove formed on the semiconductor substrate.
摘要:
The semiconductor circuit device includes a first column decoder for decoding an internal column address and generating a column select signal which selects one column, and a second column decoder for simultaneously selecting a plurality of successively adjacent columns from a memory cell array in accordance with the column select signal. The second column decoder selects the same column in a duplicated way in response to different column select signals. Since the same column is selected in a duplicate way by the different column select signals, it will be possible to simultaneously select a desired combination of a plurality of columns. A combination of a plurality of columns simultaneously selected can be arbitrarily set and a desired combination of columns can be selected with a simplified circuit structure at high speed. It will be possible to repair a column containing a defective bit without providing a redundant column by providing an input/output control circuit for further selecting a column from the columns simultaneously selected in accordance with the column select signal.
摘要:
A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of "1" is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data "1", writing of the data "1" onto the bit lines and the inversion bit lines is performed. Then, the data of "0" is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data "0", writing of the data "0" onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.
摘要:
A dynamic random access memory is disclosed which includes a trench type memory cell having a transistor formed in a semiconductive substrate, and a capacitor arranged in a trench formed in the substrate and having a trench structure. The capacitor includes an impurity-doped semiconductive layer formed on the substrate so as to surround the trench and having a conductivity type opposite to that of the substrate, a first capacitor electrode formed in the trench, and a second capacitor electrode having a portion insulatively stacked with said first capacitor electrode in the trench.
摘要:
A center hub holder tape includes a generally nonstretchable carrier tape having a series of apertures formed therethrough and spaced at an equal interval from one another along the length of the carrier tape. A series of center hubs for use in a recording disc are carried by the carrier tape, with their tubular bodies removably inserted in the apertures in the carrier tape, respectively. An adhesive layer is interposed between one side of the carrier tape and a flange around the body of the center hub to adhesively bond them together. The adhesive layer is releaseably bonded to the one side of the carrier tape so that center hub can be removed from the carrier tape together with the adhesive layer.
摘要:
In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity.
摘要:
The layout verification apparatus includes: a verification unit for obtaining mask data indicating a mask pattern to be drawn on a mask based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and for verifying a position of the mask pattern based on the mask data, so as to detect an error part; and a correction hint creating unit for creating correction hint information based on the error part, and for sending the correction hint information to a layout and wiring unit for correcting the layout and wiring data. The correction hint creating unit obtains terminal information indicating positions of a group of terminals included in the group of primitive cells and creates the correction hint information based on the terminal information so that the positions of the group of terminals are not changed by the layout and wiring unit.
摘要:
This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.