Memory device and sense amplifier control device
    91.
    发明授权
    Memory device and sense amplifier control device 失效
    存储器件和读出放大器控制器件

    公开(公告)号:US5910927A

    公开(公告)日:1999-06-08

    申请号:US931525

    申请日:1997-09-16

    摘要: A memory device having a smaller circuit area but efficiently used is provided. A plurality of main word lines (MWL) extending in a row direction are connected through respective bank latches (BL) to a single global word line (GWL) extending across banks (BANK0, BANK1). Selective activation of an enable signal (BLE) and the global word line (GWL) selects one of the bank latches (BL) to selectively activate an associated main word line (MWL). This state is held by the selected bank latch (BL) after the enable signal (BLE) is inactivated. Then, another enable signal (BLE) is activated to selectively activate another main word line (MWL). Sub-decoders (SD) connected to the main word lines (MWL) are selected independently of each other to independently activate word lines (WL) for each bank (BANK).

    摘要翻译: 提供具有较小电路面积但有效使用的存储器件。 沿着行方向延伸的多条主字线(MWL)通过相应的存储体锁存器(BL)连接到跨越银行(BANK0,BANK1)延伸的单个全局字线(GWL)。 使能信号(BLE)和全局字线(GWL)的选择性激活选择一个存储体锁存器(BL)来选择性地激活相关联的主字线(MWL)。 在使能信号(BLE)失效之后,该状态由选择的存储体锁存器(BL)保持。 然后,激活另一个使能信号(BLE)以选择性地激活另一主字线(MWL)。 连接到主字线(MWL)的子解码器(SD)彼此独立地选择,以独立地激活每个银行(BANK)的字线(WL)。

    Semiconductor memory with insulation film embedded in groove formed on
substrate
    93.
    发明授权
    Semiconductor memory with insulation film embedded in groove formed on substrate 失效
    具有绝缘膜的半导体存储器嵌入在衬底上形成的凹槽中

    公开(公告)号:US5561311A

    公开(公告)日:1996-10-01

    申请号:US350113

    申请日:1994-11-29

    摘要: A semiconductor memory having memory cells is formed on a semiconductor substrate. Each of the memory cells has a transistor and a capacitor. The transistor includes a channel region, a drain region and a source region aligned in a line and being insulated by an insulation film from an adjacent cell. Each of the memory cells has a gate electrode formed on the channel region with a gate insulating film therebetween. A pad electrode makes electrical contact with one of the source and drain regions of the memory cell and extends over the insulation film. A bit line makes electrical contact with the pad electrode above, extends in parallel to the line and is laterally isolated from one of the source and drain regions. A first insulating film is formed on the semiconductor substrate over the bit line. A first capacitor electrode is formed on the first insulating film, making electrical contact with the other of the source and drain regions of the memory cell through a contact hole opened through the first insulating film and insulated from the bit line by the first insulating film. A second capacitor electrode is formed on the first capacitor electrode with a second insulating film provided therebetween. The insulation film is embedded in a groove formed on the semiconductor substrate.

    摘要翻译: 具有存储单元的半导体存储器形成在半导体衬底上。 每个存储单元都具有晶体管和电容器。 晶体管包括沟道区域,漏极区域和源极区域,其在一条直线上排列并且被来自相邻单元格的绝缘膜绝缘。 每个存储单元具有形成在沟道区上的栅电极,其间具有栅极绝缘膜。 焊盘电极与存储单元的源区和漏区之一电接触并在绝缘膜上延伸。 位线与上面的焊盘电极电接触,平行于线延伸并且与源区和漏区之一横向隔离。 在位线上的半导体衬底上形成第一绝缘膜。 第一电容器电极形成在第一绝缘膜上,通过穿过第一绝缘膜打开的接触孔与第一绝缘膜与位线绝缘而与存储单元的另一个源极和漏极区域电接触。 在第一电容器电极上形成第二电容器电极,其间设置有第二绝缘膜。 绝缘膜嵌入形成在半导体衬底上的沟槽中。

    Semiconductor circuit device having multiplex selection functions
    94.
    发明授权
    Semiconductor circuit device having multiplex selection functions 失效
    具有多重选择功能的半导体电路设备

    公开(公告)号:US5227997A

    公开(公告)日:1993-07-13

    申请号:US708027

    申请日:1991-05-31

    CPC分类号: G11C29/808 G11C29/84

    摘要: The semiconductor circuit device includes a first column decoder for decoding an internal column address and generating a column select signal which selects one column, and a second column decoder for simultaneously selecting a plurality of successively adjacent columns from a memory cell array in accordance with the column select signal. The second column decoder selects the same column in a duplicated way in response to different column select signals. Since the same column is selected in a duplicate way by the different column select signals, it will be possible to simultaneously select a desired combination of a plurality of columns. A combination of a plurality of columns simultaneously selected can be arbitrarily set and a desired combination of columns can be selected with a simplified circuit structure at high speed. It will be possible to repair a column containing a defective bit without providing a redundant column by providing an input/output control circuit for further selecting a column from the columns simultaneously selected in accordance with the column select signal.

    摘要翻译: 半导体电路装置包括用于对内部列地址进行解码并产生选择一列的列选择信号的第一列解码器,以及第二列解码器,用于根据该列从存储单元阵列中同时选择多个相继的相邻列 选择信号。 第二列解码器以复制方式响应于不同的列选择信号选择相同的列。 由于通过不同的列选择信号以重复的方式选择相同的列,所以可以同时选择多个列的所需组合。 同时选择的多个列的组合可以任意设置,并且可以利用简单的电路结构高速选择列的期望组合。 通过提供输入/输出控制电路,可以根据列选择信号从同时选择的列进一步选择列,来修复包含有缺陷位的列而不提供冗余列。

    Content addressable semiconductor memory device and operating method
therefor
    95.
    发明授权
    Content addressable semiconductor memory device and operating method therefor 失效
    内容可寻址半导体存储器件及其操作方法

    公开(公告)号:US5126968A

    公开(公告)日:1992-06-30

    申请号:US605707

    申请日:1990-10-30

    IPC分类号: G11C15/04

    CPC分类号: G11C15/043 G11C15/04

    摘要: A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of "1" is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data "1", writing of the data "1" onto the bit lines and the inversion bit lines is performed. Then, the data of "0" is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data "0", writing of the data "0" onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.

    摘要翻译: 半导体存储器件包括多个或多个单元。 在刷新操作中,将数据“1”应用于所有位线和反转位线。 在存储数据“1”的CAM单元中,执行数据“1”到位线和反转位线的写入。 然后,将数据“0”应用于所有的位线和反转位线。 在存储数据“0”的CAM单元中,执行数据“0”到位线和反转位线的写入。 在部分写入操作中,在执行写入的CAM单元中,第一控制节点被激活,从而使得可以写入CAM单元。 在其余的CAM单元中,第一控制节点被去激活,从而不可能写入CAM单元。

    Center hub holder tape
    97.
    发明授权
    Center hub holder tape 失效
    中心轮毂支架胶带

    公开(公告)号:US4910056A

    公开(公告)日:1990-03-20

    申请号:US304626

    申请日:1989-02-01

    摘要: A center hub holder tape includes a generally nonstretchable carrier tape having a series of apertures formed therethrough and spaced at an equal interval from one another along the length of the carrier tape. A series of center hubs for use in a recording disc are carried by the carrier tape, with their tubular bodies removably inserted in the apertures in the carrier tape, respectively. An adhesive layer is interposed between one side of the carrier tape and a flange around the body of the center hub to adhesively bond them together. The adhesive layer is releaseably bonded to the one side of the carrier tape so that center hub can be removed from the carrier tape together with the adhesive layer.

    Semiconductor device and method for manufacturing the same
    98.
    发明授权
    Semiconductor device and method for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号:US07759255B2

    公开(公告)日:2010-07-20

    申请号:US11561700

    申请日:2006-11-20

    摘要: In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity.

    摘要翻译: 在本发明的一个实施例中,一种制造半导体器件的方法包括:在半导体衬底上形成被去除层; 在被去除层上形成半导体层; 在SOI区域中形成穿过所述半导体层到所述被去除层的沟槽; 通过使用沟槽去除待去除的层并产生空腔; 以及在所述空腔中形成绝缘膜。

    Layout verification apparatus, layout apparatus, layout verification method, layout verification program, and wiring forming method
    99.
    发明申请
    Layout verification apparatus, layout apparatus, layout verification method, layout verification program, and wiring forming method 审中-公开
    布局验证装置,布局装置,布局验证方法,布局验证程序和布线形成方法

    公开(公告)号:US20100115765A1

    公开(公告)日:2010-05-13

    申请号:US12585441

    申请日:2009-09-15

    申请人: Takeshi Hamamoto

    发明人: Takeshi Hamamoto

    IPC分类号: H01R43/00 G06F17/50

    CPC分类号: G06F17/5081 Y10T29/49117

    摘要: The layout verification apparatus includes: a verification unit for obtaining mask data indicating a mask pattern to be drawn on a mask based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and for verifying a position of the mask pattern based on the mask data, so as to detect an error part; and a correction hint creating unit for creating correction hint information based on the error part, and for sending the correction hint information to a layout and wiring unit for correcting the layout and wiring data. The correction hint creating unit obtains terminal information indicating positions of a group of terminals included in the group of primitive cells and creates the correction hint information based on the terminal information so that the positions of the group of terminals are not changed by the layout and wiring unit.

    摘要翻译: 布局验证装置包括:验证单元,用于基于布局布置指示要绘制的掩模图案的掩模数据,以及指示原始单元组的位置和连接到原始单元组的连接线的位置的布线数据, 并且用于基于掩模数据验证掩模图案的位置,以便检测出错误部分; 以及校正提示创建单元,用于基于所述错误部分创建校正提示信息,并且用于将校正提示信息发送到用于校正布局和布线数据的布局和布线单元。 校正提示生成单元获取指示包括在原始单元组中的一组终端的位置的终端信息,并且基于终端信息创建校正提示信息,使得该组终端的位置不被布局和布线改变 单元。

    Semiconductor memory device
    100.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US07609551B2

    公开(公告)日:2009-10-27

    申请号:US11860956

    申请日:2007-09-25

    IPC分类号: G11C14/00 G11C16/04

    摘要: This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

    摘要翻译: 本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区,其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态 通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器,将存储器从第一存储状态转移到第二存储状态 通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。