公开(公告)号：US20240347511A1

公开(公告)日：2024-10-17

申请号：US18751061

申请日：2024-06-21

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/06102 ,  H01L2224/06519 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/10253

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

公开(公告)号：US12033980B2

公开(公告)日：2024-07-09

申请号：US16871443

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/06102 ,  H01L2224/06519 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2224/141 ,  H01L2924/00012

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

公开(公告)号：US20230395463A1

公开(公告)日：2023-12-07

申请号：US18454703

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/44 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/373 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L23/44 ,  H01L25/50 ,  H01L21/563 ,  H01L24/83 ,  H01L23/3675 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0657 ,  H01L23/3736 ,  H01L24/73 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/3128 ,  H01L2924/156 ,  H01L2924/1815 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/17519 ,  H01L2224/2939 ,  H01L24/29 ,  H01L24/33 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2224/83104 ,  H01L2224/1329

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US11594462B2

公开(公告)日：2023-02-28

申请号：US16936639

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10916487B2

公开(公告)日：2021-02-09

申请号：US16505434

申请日：2019-07-08

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/427 ,  H01L23/42 ,  H01L25/065 ,  H01L23/46 ,  H01L23/473 ,  H01L23/433

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

公开(公告)号：US10861825B2

公开(公告)日：2020-12-08

申请号：US16377558

申请日：2019-04-08

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, an interconnect structure includes a first conductive element, a second conductive element, and an intermetallic palladium joint. The intermetallic palladium joint includes an intermetallic crystallite spanning between the first and second conductive elements. The intermetallic crystallite includes a first end portion and a second end portion. The first end portion directly contacts the first conductive element. The second end portion directly contacts the second conductive element.

公开(公告)号：US10741468B2

公开(公告)日：2020-08-11

申请号：US16229257

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/42 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/373

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10256216B2

公开(公告)日：2019-04-09

申请号：US16127624

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

公开(公告)号：US10224313B2

公开(公告)日：2019-03-05

申请号：US15905086

申请日：2018-02-26

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

公开(公告)号：US20190013296A1

公开(公告)日：2019-01-10

申请号：US16127624

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.