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205 条记录 (耗时 0.046 秒)

    Magnetic random access memory
    91.
    发明授权
    Magnetic random access memory 失效
    磁性随机存取存储器

    公开(公告)号：US06724653B1

    公开(公告)日：2004-04-20

    申请号：US10160058

    申请日：2002-06-04

    申请人： Yoshihisa Iwata ,  Tomoki Higashi

    发明人： Yoshihisa Iwata ,  Tomoki Higashi

    IPC分类号： G11C1100

    CPC分类号： G11C11/16 ,  G11C8/10

    摘要： A read block is constituted of a plurality of TMR elements arranged in a lateral direction. One end of each of the TMR elements in the read block is connected in common, and connected to a source line via a read select switch. The other ends of TMR elements are independently connected to read bit lines/write word lines. The read bit lines/write word lines are connected to common data lines via a row select switch. The common data lines are connected to a read circuit.

    摘要翻译： 读块由沿横向布置的多个TMR元件构成。 读块中的每个TMR元件的一端被共同连接，并通过读选择开关连接到源极线。 TMR元件的另一端独立地连接到读位线/写字线。 读取位线/写入字线通过行选择开关连接到公共数据线。 公共数据线连接到读取电路。

    Magnetic memory
    92.
    发明授权
    Magnetic memory 有权
    磁记忆

    公开(公告)号：US06717845B2

    公开(公告)日：2004-04-06

    申请号：US10345253

    申请日：2003-01-16

    申请人： Yoshiaki Saito ,  Katsuya Nishiyama ,  Shigeki Takahashi ,  Minoru Amano ,  Tomomasa Ueda ,  Hiroaki Yoda ,  Yoshiaki Asao ,  Yoshihisa Iwata ,  Tatsuya Kishi

    发明人： Yoshiaki Saito ,  Katsuya Nishiyama ,  Shigeki Takahashi ,  Minoru Amano ,  Tomomasa Ueda ,  Hiroaki Yoda ,  Yoshiaki Asao ,  Yoshihisa Iwata ,  Tatsuya Kishi

    IPC分类号： G11C1115

    CPC分类号： G11C11/16

    摘要： A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first wiring extending in a first direction on or below the magnetoresistance effect element; a covering layer provided at least both sides of the first wiring, the covering layer being made of magnetic material, and the covering layer having a uniaxial anisotropy in the first direction along which a magnetization of the covering layer occurs easily; and a writing circuit configured to pass a current through the first wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.

    摘要翻译： 磁存储器包括：具有磁记录层的磁阻效应元件; 在所述磁阻效应元件上或第二方向上延伸的第一布线; 所述覆盖层至少设置在所述第一布线的两侧，所述覆盖层由磁性材料制成，所述覆盖层在容易发生所述覆盖层的磁化的第一方向上具有单轴各向异性; 以及写入电路，被配置为使电流通过第一布线，以便通过由电流产生的磁场将信息记录在磁记录层中。

    Semiconductor integrated circuit device, method of investigating cause of failure occurring in semiconductor integrated circuit device and method of verifying operation of semiconductor integrated circuit device
    93.
    发明授权
    Semiconductor integrated circuit device, method of investigating cause of failure occurring in semiconductor integrated circuit device and method of verifying operation of semiconductor integrated circuit device 有权
    半导体集成电路器件，半导体集成电路器件中发生故障原因的方法和半导体集成电路器件的操作验证方法

    公开(公告)号：US06172930B2

    公开(公告)日：2001-01-09

    申请号：US09317167

    申请日：1999-05-24

    申请人： Yoshihisa Iwata ,  Hideko Oodaira

    发明人： Yoshihisa Iwata ,  Hideko Oodaira

    IPC分类号： G11C11404

    CPC分类号： G11C16/30

    摘要： A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.

    摘要翻译： 公开了一种NAND EEPROM，其能够为每个芯片各种地设置要施加到存储器单元的控制栅极的电压。 半导体芯片包括NAND存储单元阵列和高电压产生电路，用于产生将数据写入存储单元阵列时所需的内部电压VPP的数据写入。 此外，半导体芯片包括设定电压选择电路，用于任意设定由各芯片的高电压产生电路产生的电压VPP的电平，以及多路复用器，向芯片的外部提取设置信号LTF 用于使电压VPP的电平任意设定的信号。

    Semiconductor memory device with program/erase verification
    94.
    发明授权
    Semiconductor memory device with program/erase verification 失效
    具有编程/擦除验证的半导体存储器件

    公开(公告)号：US5761122A

    公开(公告)日：1998-06-02

    申请号：US749673

    申请日：1996-11-15

    申请人： Hiroshi Nakamura ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Keniti Imamiya

    发明人： Hiroshi Nakamura ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Keniti Imamiya

    IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： G11C16/3477 ,  G11C16/10 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3486 ,  G11C7/00

    摘要： A semiconductor memory device includes a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each, of which is arranged at one end of at least one bit line connected to the memory cell array and for latching programming data, a control section for judging whether all of a plurality of latched data included in date latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, a section for detecting potentials of the plurality of the first nodes and for judging whether all data latched by the latch circuits are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and a section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, are the same as the first data or not.

    摘要翻译： 半导体存储器件包括半导体衬底，具有存储单元的存储单元阵列，每个存储单元存储矩阵形成在半导体衬底上的数据，多个数据锁存电路，每个数据锁存电路至少布置在一端 连接到存储单元阵列的一位线和用于锁存编程数据的控制部分，用于判断包括在由多个数据锁存电路构成的日期锁存组中的多个锁存数据是否与第一数据相同的控制部分 并且用于根据判断结果控制多个第一节点的电位变化，用于检测多个第一节点的电位的部分和用于判断由锁存电路锁存的所有数据是否与第一数据相同， 用于根据判断结果控制多个第二节点的电位，以及用于检测多个第二节点和fo的电位的部分 r输出由数据锁存电路锁存的所有数据是否与第一数据相同的判断结果。

    Non-volatile semiconductor memory device
    96.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5637895A

    公开(公告)日：1997-06-10

    申请号：US523315

    申请日：1995-09-05

    申请人： Yoshihisa Iwata ,  Hiroshi Nakamura

    发明人： Yoshihisa Iwata ,  Hiroshi Nakamura

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0483

    摘要： In a non-volatile semiconductor memory device having a memory cell array formed by arranging a plurality of non-volatile reloadable semiconductor memory cells (Mi) and select gate elements on a semiconductor substrate (11) via a gate insulating film (13), each memory cell being formed by interposing an interlayer insulating film (15) between a charge storage layer and a control gate line (16.sub.i), the memory device comprises a plurality of select gate lines (14.sub.i) formed by a wiring layer the same as the charge storage layer of the memory cells, as gate electrodes of the select gate elements; and select gate over-adjacent connect lines (16.sub.9, 16.sub.10) formed by a wiring layer the same as the control gate lines (16.sub.i) of the memory cells and located over the select gate lines (14.sub.9, 14.sub.10) via an insulating film in such a way as to be kept floated without contacting with any other wires and potential nodes.

    摘要翻译： 在通过经由栅极绝缘膜（13）在半导体衬底（11）上布置多个非易失性可重载半导体存储单元（Mi）和选择栅极元件而形成的存储单元阵列的非易失性半导体存储器件中， 存储单元通过在电荷存储层和控制栅极线（16i）之间插入层间绝缘膜（15）形成，所述存储器件包括由与所述电荷相同的布线层形成的多个选择栅极线（14i） 存储单元的存储层，作为选择栅极元件的栅电极; 并且选择由与存储单元的控制栅极线（16i）相同的布线层形成的并且位于选择栅极线（149,1410）上方的栅极相邻连接线（169,1610），该绝缘膜经由绝缘膜 一种在不与任何其他电线和潜在节点接触的情况下保持浮动的方式。

    Semiconductor sense circuit suitable for buffer circuit in semiconductor memory chip
    97.
    发明授权
    Semiconductor sense circuit suitable for buffer circuit in semiconductor memory chip 失效
    半导体感应电路适用于半导体存储芯片中的缓冲电路

    公开(公告)号：US4764693A

    公开(公告)日：1988-08-16

    申请号：US48813

    申请日：1987-05-12

    申请人： Yoshihisa Iwata

    发明人： Yoshihisa Iwata

    IPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/10 ,  G11C8/06 ,  G11C11/408 ,  H03K17/04 ,  H03K3/356 ,  H03K17/687 ,  H03K19/01

    CPC分类号： G11C7/1057 ,  G11C7/065 ,  G11C7/1051 ,  G11C8/06

    摘要： A sense circuit for use in a semiconductor memory senses an input signal by comparing the input signal with a reference voltage. The sense circuit comprises a sense amplifier having first and second nodes, and first and second transfer gates. The first transfer gate couples the input signal to the first node of the sense amplifier. The second transfer gate couples the reference voltage to the second node of the sense amplifier. A level-shift circuit is provided between the second node of the sense amplifier and the second transfer gate. In response to the voltage level of the input signal latched in the first node, the level-shift circuit shifts the level of the reference voltage latched in the second node of the sense amplifier to a lower level when the input signal is high in voltage level, and shifts it to a higher level when the input signal is low in voltage level.

    摘要翻译： 用于半导体存储器的感测电路通过将输入信号与参考电压进行比较而感测输入信号。 感测电路包括具有第一和第二节点的读出放大器以及第一和第二传输门。 第一传输门将输入信号耦合到读出放大器的第一节点。 第二传输门将参考电压耦合到读出放大器的第二个节点。 在读出放大器的第二节点和第二传输门之间提供电平移位电路。 响应于在第一节点中锁存的输入信号的电压电平，当输入信号的电压电平高时，电平移位电路将读出放大器的第二节点中锁存的参考电压的电平移位到较低电平 ，并且当输入信号的电压电平低时，将其移动到更高的电平。

    Non-volatile semiconductor storage device
    99.
    发明授权
    Non-volatile semiconductor storage device 有权
    非易失性半导体存储器件

    公开(公告)号：US08203882B2

    公开(公告)日：2012-06-19

    申请号：US12718353

    申请日：2010-03-05

    申请人： Tomoo Hishida ,  Yoshihisa Iwata

    发明人： Tomoo Hishida ,  Yoshihisa Iwata

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

    摘要： When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.

    摘要翻译： 当在一个存储单元块中执行数据擦除操作时，将第一电压施加到从一个存储单元块中的m个源极线中选择的一个源极线。 在数据擦除操作开始之前等于源极线的电压的第二电压被施加到其它源极线。 然后，在施加第一电压的一定的时间延迟之后，将小于第一电压的第三电压施加到连接到所选择的源极线的源极侧选择晶体管的第三导电层。 然后，由于第一和第三电压之间的电位差，在第三栅极绝缘层附近产生空穴电流。 将第四电压施加到连接到要擦除的存储晶体管之一的第一导电层之一。 其他第一导电层进入浮置状态。