公开(公告)号：US20080203437A1

公开(公告)日：2008-08-28

申请号：US12078992

申请日：2008-04-09

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L27/11 ,  G11C11/40

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US20080143184A1

公开(公告)日：2008-06-19

申请号：US11956122

申请日：2007-12-13

申请人： Kazuo OTSUGA ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo OTSUGA ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： H02J1/00 ,  G01R19/00

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US20080114967A1

公开(公告)日：2008-05-15

申请号：US11935790

申请日：2007-11-06

申请人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

发明人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

IPC分类号： G06F9/302

CPC分类号： G06F1/3228 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device comprises: thermal sensors which can detect temperature, determine whether the detection result exceeds each of the above reference values and output the result; and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors, wherein the control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

摘要翻译： 提供了一种半导体集成电路器件，其消耗较少功率并实现实时处理。 半导体集成电路装置包括：可以检测温度的热传感器，确定检测结果是否超过上述参考值，并输出结果; 以及控制块，其能够基于所述热传感器的输出信号来控制运算块的运算，其中，所述控制块基于所述热传感器的输出信号，利用中断信号从暂停状态返回到运行状态，并且确定 运算块的操作条件，以确保运算块的温度条件得到满足。 从而降低了功耗，提高了实时处理效率。

公开(公告)号：US07336526B2

公开(公告)日：2008-02-26

申请号：US11324357

申请日：2006-01-04

申请人： Kenichi Osada ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Takayuki Kawahara

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C5/147 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79

摘要： To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.

公开(公告)号：US20070263433A1

公开(公告)日：2007-11-15

申请号：US11812641

申请日：2007-06-20

申请人： Kenichi Osada ,  Kiyoo Itoh

发明人： Kenichi Osada ,  Kiyoo Itoh

IPC分类号： G11C5/06 ,  G11C11/00 ,  G11C8/00

CPC分类号： H01L27/24 ,  G11C7/04 ,  G11C13/0004

摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.

公开(公告)号：US07251157B2

公开(公告)日：2007-07-31

申请号：US10933336

申请日：2004-09-03

申请人： Kenichi Osada ,  Kiyoo Itoh

发明人： Kenichi Osada ,  Kiyoo Itoh

IPC分类号： G11C11/00

CPC分类号： H01L27/24 ,  G11C7/04 ,  G11C13/0004

摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.

摘要翻译： 具有由垂直晶体管构成的存储单元和其中电阻值根据其上侧施加的温度而变化的存储单元的存储器块被层叠以实现高度集成的非易失性存储器。

公开(公告)号：US20070159871A1

公开(公告)日：2007-07-12

申请号：US11715918

申请日：2007-03-09

申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C7/10 ,  G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

公开(公告)号：US07206216B2

公开(公告)日：2007-04-17

申请号：US11057682

申请日：2005-02-15

申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

公开(公告)号：US20050185445A1

公开(公告)日：2005-08-25

申请号：US11057682

申请日：2005-02-15

申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

IPC分类号： G11C13/00 ,  G06F13/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C19/08 ,  H01L27/10 ,  H01L27/105

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

公开(公告)号：US06839268B2

公开(公告)日：2005-01-04

申请号：US10686569

申请日：2003-10-17

申请人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

发明人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

IPC分类号： G11C11/413 ,  G06F12/08 ,  G11C7/06 ,  G11C7/18 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： G11C7/18 ,  G06F12/0802 ,  G11C7/065

摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.