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241 条记录 (耗时 0.045 秒)

    Structures and methods of a bistable resistive random access memory
    91.
    发明授权
    Structures and methods of a bistable resistive random access memory 有权
    双稳态电阻随机存取存储器的结构和方法

    公开(公告)号：US08129706B2

    公开(公告)日：2012-03-06

    申请号：US11381973

    申请日：2006-05-05

    申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L29/04 ,  H01L47/00

    CPC分类号： H01L27/101 ,  H01L27/24 ,  H01L45/04 ,  H01L45/145

    摘要： Structures and methods to form a bistable resistive random access memory for reducing the amount of heat dissipation from electrodes by confining a heating region in the memory cell device are described. The heating region is confined in a kernel comprising a programmable resistive memory material that is in contact with an upper programmable resistive memory member and a lower programmable resistive memory member. The lower programmable resistive member has sides that align with sides of a bottom electrode comprising a tungsten plug. The lower programmable resistive member and the bottom electrode function a first conductor so that the amount of heat dissipation from the first conductor is reduced. The upper programmable resistive memory material and a top electrode function as a second conductor so that the amount of heat dissipation from the second conductor is reduced.

    摘要翻译： 描述了形成双稳态电阻随机存取存储器的结构和方法，用于通过将加热区限制在存储单元装置中来减少从电极散热的量。 加热区域被限制在包括与上可编程电阻存储器构件和下可编程电阻存储器构件接触的可编程电阻性存储器材料的内核中。 下部可编程电阻构件具有与包括钨插件的底部电极的侧面对准的侧面。 下可编程电阻构件和底电极起第一导体的作用，使得来自第一导体的散热量减小。 上部可编程电阻性存储器材料和顶部电极用作第二导体，使得来自第二导体的散热量减少。

    Low hydrogen concentration charge-trapping layer structures for non-volatile memory
    92.
    发明授权
    Low hydrogen concentration charge-trapping layer structures for non-volatile memory 有权
    用于非易失性存储器的低氢浓度电荷捕获层结构

    公开(公告)号：US08022465B2

    公开(公告)日：2011-09-20

    申请号：US11274781

    申请日：2005-11-15

    申请人： Yen-Hao Shih ,  Min-Ta Wu ,  Shin-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： Yen-Hao Shih ,  Min-Ta Wu ,  Shin-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518

    摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.

    摘要翻译： 存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

    Resistance random access memory
    94.
    发明授权
    Resistance random access memory 有权
    电阻随机存取存储器

    公开(公告)号：US07989790B2

    公开(公告)日：2011-08-02

    申请号：US11656246

    申请日：2007-01-18

    申请人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang-Yeu Hsieh

    发明人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang-Yeu Hsieh

    IPC分类号： H01L47/00

    CPC分类号： H01L27/24 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C16/0475 ,  G11C2213/31 ,  G11C2213/51

    摘要： A memory comprises a number of word lines in a first direction, a number of bit lines in a second direction, each coupled to at least one of the word lines, and a number of memory elements, each coupled to one of the word lines and one of the bit lines. Each memory element comprises a top electrode for connecting to a corresponding word line, a bottom electrode for connecting to a corresponding bit line, a resistive layer on the bottom electrode, and at least two separate liners, each liner having resistive materials on both ends of the liner and each liner coupled between the top electrode and the resistive layer.

    摘要翻译： 存储器包括在第一方向上的多个字线，第二方向上的多个位线，每个字线连接到至少一个字线，以及多个存储器元件，每个存储器元件耦合到字线之一， 其中一个位线。 每个存储元件包括用于连接到对应的字线的顶部电极，用于连接到对应的位线的底部电极，底部电极上的电阻层，以及至少两个分离的衬垫，每个衬垫在两端具有电阻材料 衬垫和每个衬垫耦合在顶部电极和电阻层之间。

    BRIDGE RESISTANCE RANDOM ACCESS MEMORY DEVICE AND METHOD WITH A SINGULAR CONTACT STRUCTURE
    98.
    发明申请
    BRIDGE RESISTANCE RANDOM ACCESS MEMORY DEVICE AND METHOD WITH A SINGULAR CONTACT STRUCTURE 有权
    桥接电阻随机接入存储器件和具有单一接触结构的方法

    公开(公告)号：US20100015757A1

    公开(公告)日：2010-01-21

    申请号：US12558401

    申请日：2009-10-02

    申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L21/06

    CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    摘要： A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.

    摘要翻译： 公开了一种桥结构中的电阻随机存取存储器，其包括其中第一和第二电极位于接触结构内的接触结构。 第一电极具有围绕接触结构的内壁的周向延伸形状，例如环形形状。 第二电极位于周向延伸形状的内部，并通过绝缘材料与第一电​​极分离。 电阻记忆桥与第一和第二电极的边缘表面接触。 接触结构中的第一电极连接到晶体管，并且接触结构中的第二电极连接到位线。 位线通过自对准工艺连接到第二电极。

    METHODS OF OPERATING A BISTABLE RESISTANCE RANDOM ACCESS MEMORY WITH MULTIPLE MEMORY LAYERS AND MULTILEVEL MEMORY STATES
    99.
    发明申请
    METHODS OF OPERATING A BISTABLE RESISTANCE RANDOM ACCESS MEMORY WITH MULTIPLE MEMORY LAYERS AND MULTILEVEL MEMORY STATES 有权
    具有多个存储层和多个存储器状态的双向电阻随机存取存储器的操作方法

    公开(公告)号：US20090303774A1

    公开(公告)日：2009-12-10

    申请号：US12511846

    申请日：2009-07-29

    申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： G11C11/00

    CPC分类号： G11C17/165 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C17/16 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77

    摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.

    摘要翻译： 描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。 双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。 四个不同逻辑状态之间的关系可以由两个变量n和f以及电阻R在数学上表示。逻辑“0”状态由数学表达式（1 + f）R表示。 逻辑“1”状态由数学表达式（n + f）R表示。 逻辑“2”状态由数学表达式（1 + nf）R表示。 逻辑“3”状态由数学表达式n（1 + f）R表示。