公开(公告)号：US20210193197A1

公开(公告)日：2021-06-24

申请号：US16953207

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20210098280A1

公开(公告)日：2021-04-01

申请号：US17068717

申请日：2020-10-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

IPC: H01L21/768 ,  H01L25/065

Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.

公开(公告)号：US20210049118A1

公开(公告)日：2021-02-18

申请号：US16921061

申请日：2020-07-06

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/10 ,  G11C7/22 ,  G06F1/06 ,  G06F1/08 ,  G06F1/04

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US10804139B2

公开(公告)日：2020-10-13

申请号：US15824762

申请日：2017-11-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

IPC: H01L21/768 ,  H01L25/065

Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.

公开(公告)号：US10705990B2

公开(公告)日：2020-07-07

申请号：US16228695

申请日：2018-12-20

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/16 ,  G11C7/22 ,  G11C7/04 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US10339990B2

公开(公告)日：2019-07-02

申请号：US15665312

申请日：2017-07-31

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G01C7/02 ,  G11C7/22 ,  G06F13/16 ,  G11C7/02

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US10249353B2

公开(公告)日：2019-04-02

申请号：US15604251

申请日：2017-05-24

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Lei Luo

IPC: G06F13/12 ,  G11C7/22 ,  G11C7/10 ,  G06F13/42 ,  G06F1/08 ,  G06F13/16 ,  G06F13/40

Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

公开(公告)号：US20190052269A1

公开(公告)日：2019-02-14

申请号：US16051291

申请日：2018-07-31

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/00 ,  G06F3/06 ,  G06F13/40 ,  G11C16/06 ,  G11C11/417 ,  G11C16/32 ,  G11C11/413 ,  G11C11/4063 ,  G11C11/401 ,  G11C11/41 ,  G11C16/26 ,  G11C11/419 ,  H03K19/0175 ,  G11C11/4093

Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

公开(公告)号：US20170331477A1

公开(公告)日：2017-11-16

申请号：US15581480

申请日：2017-04-28

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/06 ,  G11C11/419 ,  G11C11/417 ,  G11C11/413 ,  G11C11/41 ,  G11C11/4093 ,  G11C11/4063 ,  G11C11/401 ,  G06F13/40 ,  G11C16/32 ,  H03K19/0175

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

公开(公告)号：US20170249265A1

公开(公告)日：2017-08-31

申请号：US15458166

申请日：2017-03-14

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F1/32 ,  G06F13/40

CPC classification number: G06F13/1678 ,  G06F1/3275 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.