公开(公告)号：US06777774B2

公开(公告)日：2004-08-17

申请号：US10125244

申请日：2002-04-17

申请人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

发明人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

IPC分类号： H01L2900

CPC分类号： H01L28/10 ,  H01L23/552 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.

摘要翻译： 公开了一种半导体上的新型有用屏蔽电感器。 电浮动高电阻材料的区域沉积在电感器和半导体衬底之间。 高电阻屏蔽层被图案化为多个间隙，使得由电感器在屏蔽层中感应的电流不具有闭环路径。 高电阻浮动屏蔽补充了接地的低电阻屏蔽以实现更高性能的电感器。 以这种方式，衬底中的噪声降低。 新型互补屏蔽不会显着降低电感器的品质因数，如品质因数和谐振频率。 在一个实施例中，接地屏蔽由图案化的N阱（或P阱）结构制成。 在另一个实施例中，低电阻电接地屏蔽由图案化的硅化物制成，其可以形成在衬底本身的部分上。

公开(公告)号：US06566650B1

公开(公告)日：2003-05-20

申请号：US09664418

申请日：2000-09-18

申请人： Chang Chaun Hu ,  Kin Leong Pey ,  Yung Fu Chong ,  Chim Wai Kin ,  Pavel Neuzil ,  Lap Chan

发明人： Chang Chaun Hu ,  Kin Leong Pey ,  Yung Fu Chong ,  Chim Wai Kin ,  Pavel Neuzil ,  Lap Chan

IPC分类号： B01D5944

CPC分类号： G01Q60/58 ,  Y10S977/867 ,  Y10S977/875

摘要： One of the limitations to current usage of scanning thermal microscopes arises when one needs to obtain a thermal map of an electrically biased specimen. Current practice is for the conductive parts of the specimen to be passivated to prevent excessive current leakage between the tip and the conductive sample. The present invention eliminates the need for this by coating the probe's microtip with a layer of insulation that is also a good thermal conductor. Examples of both thermocouple and thermistor based probes are given along with processes for their manufacture.

摘要翻译： 当需要获得电偏置样本的热图时，会出现当前使用扫描热显微镜的局限性。 目前的做法是使样品的导电部件被钝化，以防止尖端和导电样品之间的过大的电流泄漏。 本发明通过用也是良好热导体的绝缘层涂覆探针的微尖头来消除对此的需要。 给出了热电偶和基于热敏电阻的探针的实例以及其制造方法。

公开(公告)号：US06544824B1

公开(公告)日：2003-04-08

申请号：US10038390

申请日：2002-01-03

申请人： Yelehanka Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung

发明人： Yelehanka Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung

IPC分类号： H01L2100

CPC分类号： H01L29/66666

摘要： A method of manufacturing a vertical transistor. A doped region is formed in a substrate. We form sequentially on the substrate: a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. A trench is formed through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. A gate dielectric layer is formed over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. A cap layer is formed over the structure. Contacts are preferably formed to the doped region, doped layers and gate electrodes.

摘要翻译： 一种垂直晶体管的制造方法。 在衬底中形成掺杂区域。 我们在衬底上依次形成：第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层。 通过第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层形成沟槽。 沟槽有侧壁。 栅极电介质层形成在沟槽的侧壁上。 我们在沟槽中依次形成：第一掺杂层，第一沟道层，第二掺杂层，第三掺杂层，第二沟道层和第四掺杂层。 在该结构上形成盖层。 触点优选地形成于掺杂区域，掺杂层和栅电极。

公开(公告)号：US06468877B1

公开(公告)日：2002-10-22

申请号：US09907651

申请日：2001-07-19

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

IPC分类号： H01L2176

CPC分类号： H01L21/7682 ,  H01L21/764 ,  H01L21/823468 ,  H01L29/4983

摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.

摘要翻译： 一种制造半导体器件的气隙间隔物的方法，包括以下步骤。 提供具有至少一对限定有源区域的STI的半导体衬底。 在有源区内的基板上形成栅电极。 栅电极具有底层栅介电层。 在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。 在衬垫氧化物层上形成衬里氮化物层。 在结构上形成厚的氧化物层。 厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。 用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。 在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。 蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。 栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

公开(公告)号：US06455377B1

公开(公告)日：2002-09-24

申请号：US09765040

申请日：2001-01-19

申请人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

发明人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/1054 ,  H01L29/66916 ,  H01L29/7827 ,  H01L29/802

摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.

摘要翻译： 一种制造垂直沟道晶体管的方法，包括以下步骤。 提供具有上表面的半导体衬底。 在半导体衬底上形成高掺杂N型下部外延硅层。 在下部外延硅层上形成低掺杂P型中间外延硅层。 在中间外延硅层上形成高掺杂N型上部外延硅层。 蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。 在隔离槽内形成氧化物。 氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。 在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。 在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。 栅极导体层形成在栅极电介质层上，填充栅极沟槽。

公开(公告)号：US06440800B1

公开(公告)日：2002-08-27

申请号：US09769814

申请日：2001-01-26

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/365 ,  H01L29/7827

摘要： A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

公开(公告)号：US06281117B1

公开(公告)日：2001-08-28

申请号：US09425994

申请日：1999-10-25

申请人： Lap Chan ,  Chaw Sing Ho ,  Fong Yau Sam Li ,  Hou Tee Ng

发明人： Lap Chan ,  Chaw Sing Ho ,  Fong Yau Sam Li ,  Hou Tee Ng

IPC分类号： H01L214763

CPC分类号： H01L21/28518 ,  Y10S977/859

摘要： A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted. Or the metal acetate layer is heat treated at localized regions using a multi-array of tips aligned in a specific layout. Or the metal acetate layer is contacted by heated metallic tips under vacuum so that the metal does not oxidize. The unreacted metal acetate layer is removed leaving the metal silicide as the uniform ultrathin silicide features.

摘要翻译： 描述了在制造集成电路中形成均匀的超薄硅化物特征的方法。 金属层沉积在硅半导体衬底的表面上。 加热的金属尖端的阵列接触金属层，由此将金属层转变为金属硅化物，在金属硅化物中金属层与金属顶端接触，并且其中不与金属尖端接触的金属层是未反应的。 除去未反应的金属层，留下金属硅化物作为均匀的超薄硅化物特征。 或者，将金属乙酸盐层旋涂在硅半导体衬底的表面上。 加热的金属尖端的阵列接触金属乙酸盐层，由此金属乙酸盐层转变为金属硅化物，其中金属尖端与金属乙酸盐层接触，并且其中未与金属尖端接触的金属乙酸盐钝化剂未反应。 或者使用在特定布局中对齐的多阵列尖端在局部区域对金属乙酸盐层进行热处理。 或者金属乙酸盐层在真空下被加热的金属尖端接触，使得金属不氧化。 除去未反应的金属乙酸盐层，留下金属硅化物作为均匀的超薄硅化物特征。

公开(公告)号：US06252277B1

公开(公告)日：2001-06-26

申请号：US09392392

申请日：1999-09-09

申请人： Lap Chan ,  Cher Liang Cha ,  Eng Fong Chor ,  Gong Hao ,  Teck Koon Lee

发明人： Lap Chan ,  Cher Liang Cha ,  Eng Fong Chor ,  Gong Hao ,  Teck Koon Lee

IPC分类号： H01L2972

CPC分类号： H01L29/66621 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834

摘要： Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed. The new process, uses the same total number of photolithographic steps to form the MOSFET device elements as a conventional process but is far more protective of the thin gate oxide.

摘要翻译： 描述了形成具有嵌入在硅沟槽内的多晶硅栅电极的MOSFET。 MOSFET保留了具有光刻图案化多晶硅栅电极的常规MOSFET的所有特征，包括沿沟槽壁形成的鲁棒LDD（轻掺杂漏极）区域。 因为栅极电介质永远不会暴露于等离子体蚀刻或水性化学蚀刻，所以可以形成低于100埃的栅介质膜而没有缺陷。 在光刻图案化多晶硅栅电极的制造中遇到的过蚀刻和衬底尖峰的问题不会发生。 整个过程仅使用两个光刻步骤。 第一步骤通过图案化场隔离来定义硅有源面积，第二步限定在形成器件的有源区域内的沟槽。 新工艺使用相同的光刻步骤总数来形成MOSFET器件元件作为常规工艺，但对薄栅极氧化物的保护更为广泛。

公开(公告)号：US06251798B1

公开(公告)日：2001-06-26

申请号：US09359894

申请日：1999-07-26

申请人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

发明人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

IPC分类号： H01L2131

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.

摘要翻译： 一种用于形成用于金属间应用的气隙结构的方法。 形成金属线的金属图案，在该图案的顶部上沉积一层等离子聚合甲基硅烷（PPMS）抗蚀剂。 对PPMS抗蚀剂的表面进行选择性曝光。 未曝光的PPMS被去除，之后通过关闭PPMS内的开口来完成该过程。

公开(公告)号：US06251781B1

公开(公告)日：2001-06-26

申请号：US09374312

申请日：1999-08-16

申请人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

发明人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L21/76874 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating single and dual damascene copper interconnects is achieved. A semiconductor substrate layer is provided. Conductive traces are provided in an isolating dielectric layer. An intermetal dielectric layer is deposited overlying the conductive traces and the isolating dielectric layer. The intermetal dielectric layer is patterned to form trenches to expose the top surfaces of the underlying conductive traces. A barrier layer is deposited overlying the intermetal dielectric layer, the exposed conductive traces, and within the trenches. A platinum ionic seed solution is coated inside the trenches and overlying the barrier layer. A platinum seed layer is deposited from the ionic seed solution by exposing the platinum ionic seed solution to ultraviolet light. A copper layer is deposited by electroless plating to form copper interconnects, where the copper layer is only deposited overlying the platinum seed layer in the trenches, and where the deposition stops before the copper layer fills the trenches. The exposed barrier layer is polished down to the top surface of the intermetal dielectric layer. An encapsulation layer is deposited overlying the copper interconnects and the intermetal dielectric layer to complete the fabrication of the integrated circuit device.

摘要翻译： 实现了制造单和双镶嵌铜互连的方法。 提供半导体衬底层。 导电迹线设置在隔离电介质层中。 沉积覆盖导电迹线和隔离电介质层的金属间电介质层。 图案化金属间电介质层以形成沟槽以暴露下面的导电迹线的顶表面。 覆盖在金属间电介质层，暴露的导电迹线和沟槽内的阻挡层被沉积。 将铂离子种子溶液涂覆在沟槽内并覆盖阻挡层。 通过将铂离子种子溶液暴露于紫外光，从离子种子溶液沉积铂种子层。 通过无电镀沉积铜层以形成铜互连，其中铜层仅沉积在沟槽中的铂种子层上方，并且在铜层填充沟槽之前沉积停止。 暴露的阻挡层被抛光到金属间电介质层的顶表面。 沉积覆盖在铜互连和金属间电介质层上的封装层，以完成集成电路器件的制造。