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    Integrated circuits and methods for fabricating integrated circuits with improved contact structures
    92.
    发明授权
    Integrated circuits and methods for fabricating integrated circuits with improved contact structures 有权
    用于制造具有改进的接触结构的集成电路的集成电路和方法

    公开(公告)号：US09373542B2

    公开(公告)日：2016-06-21

    申请号：US14081749

    申请日：2013-11-15

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Xunyuan Zhang ,  Xiuyu Cai ,  Hoon Kim

    IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/285

    CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.

    Abstract translation: 提供具有改进的接触结构的集成电路和用于制造具有改进的接触结构的集成电路的方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底内和/或半导体衬底上提供器件。 此外，该方法包括形成与该装置电接触的接触结构。 接触结构包括覆盖该装置的硅酸盐阻挡部分，覆盖该装置并且位于硅酸盐阻挡部分之间的阻挡金属以及覆盖该阻挡金属并位于硅酸盐阻挡部分之间的填充金属。

    SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES
    94.
    发明申请
    SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES 审中-公开
    具有更换门结构的半导体器件

    公开(公告)号：US20160093713A1

    公开(公告)日：2016-03-31

    申请号：US14963378

    申请日：2015-12-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

    IPC: H01L29/51 ,  H01L29/78

    CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

    Abstract: A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material.

    Abstract translation: 晶体管器件包括半导体衬底和位于半导体衬底表面之上的栅极结构。 栅极结构包括位于半导体衬底的表面上方的高k栅极绝缘层和位于高k栅极绝缘层上方的材料的至少一个功函数调节层，其中该至少一个工件的上表面 当在晶体管器件的栅极宽度方向上截取的横截面中观察时，材料的功能调节层具有阶梯形轮廓。 栅极结构还包括位于至少一个功函数调节层材料的阶梯状上表面上的导电材料层。

    Integrated circuits having gate cap protection and methods of forming the same
    95.
    发明授权
    Integrated circuits having gate cap protection and methods of forming the same 有权
    具有栅极盖保护的集成电路及其形成方法

    公开(公告)号：US09269611B2

    公开(公告)日：2016-02-23

    申请号：US14159944

    申请日：2014-01-21

    Applicant: GLOBALFOUNDRIES, Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Daniel Thanh Khae Pham ,  Xiuyu Cai ,  Bala Subramanian Pranatharthi Haran ,  Charan Veera Venkata Satya Surisetty ,  Jin Wook Lee ,  Shom Ponoth ,  David V. Horak

    IPC: H01L29/78 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.

    Abstract translation: 提供了形成集成电路的集成电路和方法。 集成电路包括覆盖基底的栅电极结构。 栅极电极结构包括栅电极，栅极设置在栅电极上，侧壁间隔件邻近栅电极结构的侧壁设置。 源极和漏极区域形成在与栅电极结构对准的基底衬底中。 第一电介质层设置成与侧壁间隔物相邻。 侧壁间隔件和盖在第一电介质层的顶表面下方具有凹陷表面，并且保护层设置在凹入表面之上。 第二电介质层设置在第一电介质层和保护层之上。 电互连通过第一介电层和第二介电层设置，并且电互连与相应的源区和漏区电连通。

    METHODS OF FORMING MIS CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES BY SELECTIVE DEPOSITION OF INSULATING MATERIAL AND THE RESULTING DEVICES
    96.
    发明申请
    METHODS OF FORMING MIS CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES BY SELECTIVE DEPOSITION OF INSULATING MATERIAL AND THE RESULTING DEVICES 审中-公开
    通过绝缘材料的选择性沉积和结晶器件形成半导体器件的接触结构的方法

    公开(公告)号：US20160049370A1

    公开(公告)日：2016-02-18

    申请号：US14457370

    申请日：2014-08-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal Kamineni ,  Xiuyu Cai ,  Xunyuan Zhang

    IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76831 ,  H01L21/285 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method disclosed herein includes, among other things, forming at least one layer of insulating material above a semiconductor layer, performing at least one contact opening etching process to form a contact opening in the at least one layer of insulating material that exposes a portion of the semiconductor layer, selectively depositing a metal-oxide insulating material through the contact opening on the exposed surface of the semiconductor layer, and forming a conductive contact in the contact opening that contacts the metal-oxide insulating material.

    Abstract translation: 本文公开的一种方法包括在半导体层之上形成至少一层绝缘材料，执行至少一个接触开口蚀刻工艺，以在所述至少一层绝缘材料中形成接触开口，该绝缘材料层暴露一部分 半导体层，通过半导体层的暴露表面上的接触开口选择性地沉积金属氧化物绝缘材料，并且在与金属氧化物绝缘材料接触的接触开口中形成导电接触。

    FinFET semiconductor devices with local isolation features and methods for fabricating the same
    97.
    发明授权
    FinFET semiconductor devices with local isolation features and methods for fabricating the same 有权
    具有局部隔离特性的FinFET半导体器件及其制造方法

    公开(公告)号：US09245979B2

    公开(公告)日：2016-01-26

    申请号：US13902369

    申请日：2013-05-24

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Songkram Srivathanakul

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66795 ,  H01L29/7851

    Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.

    Abstract translation: 提供具有局部隔离特征的FinFET半导体器件和用于制造这种器件的方法。 在一个实施例中，制造半导体器件的方法包括提供包括形成在其上的多个翅片结构的半导体衬底，其中，所述多个翅片结构中的每一个具有侧壁，围绕所述多个翅片结构的侧壁形成间隔件，以及形成 位于所述半导体衬底上并位于所述多个翅片结构之间的含硅层。 该方法还包括移除含硅层的至少第一部分以形成多个空隙区域，同时至少留下第二部分，并在多个空隙区域中沉积隔离材料。

    Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices
    98.
    发明授权
    Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices 有权
    使用替代栅极技术形成finFET半导体器件的方法和所得到的器件

    公开(公告)号：US09236480B2

    公开(公告)日：2016-01-12

    申请号：US14044120

    申请日：2013-10-02

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

    CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    Abstract: One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.

    Abstract translation: 所公开的一种方法包括在第一和第二散热片之间形成凸起的隔离柱结构，其中所述凸起的隔离柱结构分别部分地限定所述第一和第二鳍之间的第一和第二空间，并且形成围绕所述第一和第二鳍的栅极结构 和第二鳍片和凸起的隔离柱结构，其中栅极结构的至少一部分位于第一和第二空间中。 一个说明性装置尤其包括第一和第二散热片，位于第一和第二散热片之间的凸起的隔离柱结构，由翅片和凸起的隔离柱结构限定的第一和第二空间以及围绕一部分 的翅片和隔离柱结构。

    Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
    100.
    发明授权
    Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance 有权
    用于制造具有减小的寄生电容的集成电路的集成电路和方法

    公开(公告)号：US09190486B2

    公开(公告)日：2015-11-17

    申请号：US13682331

    申请日：2012-11-20

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Xunyuan Zhang

    IPC: H01L21/76 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

    CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/78

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成牺牲栅极结构。 在牺牲栅极结构周围形成间隔物，并且在间隔物和半导体衬底上沉积电介质材料。 该方法包括选择性地蚀刻间隔物以在牺牲栅极结构和电介质材料之间形成沟槽。 沟槽由沟槽表面限定，在该沟槽表面上沉积替代间隔物材料。 该方法合并替换间隔物材料的上部区域以在替换间隔物材料内包围空隙。

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