公开(公告)号：US20120181551A1

公开(公告)日：2012-07-19

申请号：US13348781

申请日：2012-01-12

申请人： Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/24

CPC分类号： H01L21/0475 ,  H01L29/045 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66068

摘要： A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate and a trench. The silicon carbide semiconductor substrate has an offset angle with respect to a (0001) plane or a (000-1) plane and has an offset direction in a direction. The trench is provided from a surface of the silicon carbide semiconductor substrate. The trench extends in a direction whose interior angle with respect to the offset direction is 30 degrees or −30 degrees.

摘要翻译： 碳化硅半导体器件包括碳化硅半导体衬底和沟槽。 碳化硅半导体衬底相对于（0001）面或（000-1）面具有偏移角，并且在<11-20>方向上具有偏移方向。 从碳化硅半导体衬底的表面提供沟槽。 沟槽沿相对于偏移方向的内角为30度或-30度的方向延伸。

公开(公告)号：US20110316049A1

公开(公告)日：2011-12-29

申请号：US13254638

申请日：2009-03-02

申请人： Masahiro Sugimoto ,  Narumasa Soejima ,  Tsutomu Uesugi ,  Masahito Kodama ,  Eiko Ishii

发明人： Masahiro Sugimoto ,  Narumasa Soejima ,  Tsutomu Uesugi ,  Masahito Kodama ,  Eiko Ishii

IPC分类号： H01L29/778 ,  H01L21/20

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7788

摘要： Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device, which is a vertical HEMT, is provided with an n− type GaN first nitride semiconductor layer, p+ type GaN second nitride semiconductor layers, an n− type GaN third nitride semiconductor layer, and an n− type AlGaN fourth nitride semiconductor layer that is in hetero junction with a front surface of the third nitride semiconductor layer. Openings that penetrate the third nitride semiconductor layer and reach front surfaces of the second nitride semiconductor layers are provided at positions isolated from the peripheral edge of the third nitride semiconductor layer. Source electrodes are provided in the openings. Etching damage that is in contact with the source electrodes is surrounded by a region where no etching damage is formed.

摘要翻译： 提供了可以抑制泄漏电流的发生的垂直氮化物半导体器件，以及这种氮化物半导体器件的制造方法。 作为垂直HEMT的氮化物半导体器件设置有n型GaN第一氮化物半导体层，p +型GaN第二氮化物半导体层，n型GaN第三氮化物半导体层和n型AlGaN第四氮化物半导体层 半导体层，其与第三氮化物半导体层的前表面处于异质结。 穿过第三氮化物半导体层并到达第二氮化物半导体层的前表面的开口设置在与第三氮化物半导体层的外围边缘隔离的位置处。 源电极设置在开口中。 与源电极接触的蚀刻损伤被没有形成蚀刻损伤的区域包围。

公开(公告)号：US20110309464A1

公开(公告)日：2011-12-22

申请号：US13164246

申请日：2011-06-20

申请人： Kensaku YAMAMOTO ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku YAMAMOTO ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/06

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/8613

摘要： A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.

摘要翻译： 半导体器件包括半导体衬底和电场端子部分。 半导体衬底包括衬底，设置在衬底的表面上的漂移层和设置在漂移层的表面上的基底层。 半导体衬底被分成其中设置半导体元件的单元区域和围绕单元区域的外围区域。 基底区域具有位于整个电池区域和外围区域的同一平面上的底面，并且提供位于周边区域中的电场弛豫层。 电场端子部围绕电池区域和电场缓和层的一部分，从电场缓和层的表面向漂移层贯通电场缓和层。

公开(公告)号：US20080149964A1

公开(公告)日：2008-06-26

申请号：US11795117

申请日：2006-01-20

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/778

CPC分类号： H01L29/452 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.

摘要翻译： 半导体器件10包括由p型氮化镓制成的下半导体层26和由n型AlGaN制成的上半导体层28之间的异质结，其中上半导体层28具有比下半导体层26更大的带隙 。 半导体器件10还包括形成在上半导体层28的顶表面的一部分上的漏电极32，形成在上半导体层28的顶表面的不同部分上的源极34和栅电极36 电连接到下半导体层26。 半导体器件10可以正常工作。

公开(公告)号：US20080128862A1

公开(公告)日：2008-06-05

申请号：US11667735

申请日：2005-11-14

申请人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

发明人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

IPC分类号： H01L21/20 ,  H01L29/20

CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/41 ,  H01L29/778 ,  H01L29/7788 ,  H01L29/8122

摘要： A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

摘要翻译： 半导体器件设置有漏电极22，半导体基板32，覆盖半导体基板32的一部分表面的电流调节层42，并在半导体基板的表面留下未被覆盖的表面55 板32，覆盖电流调节层42的表面的半导体层50和形成在半导体层50的表面的源电极62。 在半导体层50内形成有漂移区56，沟道形成区54和源极区52。 漏电极22连接到电源的第一端子，源电极62连接到电源的第二端子。 利用该半导体层50，可以提高耐压或减少电流泄漏的发生。

公开(公告)号：US20050200875A1

公开(公告)日：2005-09-15

申请号：US11068870

申请日：2005-03-02

申请人： Masahiro Sugimoto ,  Satoru Moriyama

发明人： Masahiro Sugimoto ,  Satoru Moriyama

IPC分类号： B41J29/38 ,  B41J11/00 ,  B41J15/04 ,  G06F3/12 ,  G06F15/00 ,  H04N1/46

CPC分类号： B41J11/009 ,  B41J15/042

摘要： If a signal of a unit detecting switch provided at a roll paper unit setting position in a print apparatus is detected and the value indicated by the detected signal is not stored in a medium information memory area, it is determined that it is a new roll paper unit and shortage request information is transmitted to a personal computer. If medium information is received, a medium information acquisition processing is carried out. In this medium information acquisition processing, received medium information is stored in the medium information memory area.

摘要翻译： 如果检测到设置在打印设备中的卷纸单元设置位置处的单元检测开关的信号，并且检测到的信号指示的值未被存储在介质信息存储区域中，则确定它是新的卷纸 单位和短缺请求信息被传送到个人计算机。 如果接收到媒体信息，则进行介质信息获取处理。 在该介质信息获取处理中，接收的介质信息被存储在介质信息存储区域中。

公开(公告)号：US5929385A

公开(公告)日：1999-07-27

申请号：US850184

申请日：1997-05-02

申请人： Masahiro Sugimoto ,  Akio Kimura ,  Masanao Mimura ,  Hideo Ishii ,  Shoichi Honjo ,  Yoshihiro Iwata

发明人： Masahiro Sugimoto ,  Akio Kimura ,  Masanao Mimura ,  Hideo Ishii ,  Shoichi Honjo ,  Yoshihiro Iwata

IPC分类号： H01L39/14 ,  H01B12/00

CPC分类号： H01L39/143

摘要： Disclosed is an AC oxide superconductor round wire including a metal matrix, and a plurality of superconductor filaments embedded in the metal matrix, wherein the superconductor filaments are twisted at a twist pitch L.sub.p satisfying the following relation.2L.sub.c1

摘要翻译： 公开了一种包含金属基体的AC氧化物超导体圆线和嵌入在金属基体中的多根超导体丝，其中超导体长丝以满足以下关系的扭曲节距Lp扭曲.2Lc1

公开(公告)号：US5096749A

公开(公告)日：1992-03-17

申请号：US588862

申请日：1990-09-27

申请人： Shigeki Harada ,  Masahiro Sugimoto

发明人： Shigeki Harada ,  Masahiro Sugimoto

IPC分类号： C23C14/06 ,  C04B41/51 ,  C04B41/52 ,  C04B41/89 ,  C23C14/14 ,  C23C14/18 ,  C23C14/58 ,  H01L23/10 ,  H05K1/03 ,  H05K3/38

CPC分类号： C04B41/009 ,  C04B41/52 ,  C04B41/89 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2924/01047 ,  H01L2924/10253 ,  H01L2924/207 ,  H05K1/0306 ,  H05K3/38 ,  Y10T428/12056 ,  Y10T428/12576 ,  Y10T428/31536

摘要： A metallization layer structure containing, in order, an aluminum nitride ceramic base layer, an aluminum titanium nitride layer, a titanium layer, a heat-resistant metallic layer and a metallic layer for facilitating soldering and brazing. The aluminum titanium nitride layer is formed at the interface between the aluminum nitride ceramic base layer and the titanium layer by subjecting a laminate containing, in order, an aluminum nitride ceramic base layer, a titanium layer, a heat-resistant metallic layer and a metallic layer for facilitating soldering and brazing to a heat treatment within the range of 350.degree.-1000.degree. C. for 40 minutes.

公开(公告)号：US5081067A

公开(公告)日：1992-01-14

申请号：US698030

申请日：1991-05-10

申请人： Nobutaka Shimizu ,  Takehisa Tsujimura ,  Masahiro Sugimoto ,  Shigeki Harada

发明人： Nobutaka Shimizu ,  Takehisa Tsujimura ,  Masahiro Sugimoto ,  Shigeki Harada

IPC分类号： H01L23/04 ,  H01L23/057 ,  H01L23/367 ,  H01L23/498

CPC分类号： H01L23/04 ,  H01L23/057 ,  H01L23/367 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/15312 ,  Y10T29/49144

摘要： A ceramic package type semiconductor device comprising: a ceramic substrate having a wiring pattern layer formed on a top surface thereof; at least one semiconductor element mounted on the ceramic substrate with a top face thereof facing downward and electrically connected to the wiring patttern layer; a metal cap having at least one through-hole corresponding to an external size of the semiconductor element and an end portion thereof soldered to the top surface of the ceramic substrate, so that a top surface of the metal cap and a bottom surface of the semiconductor element fitting into the through-hole form a flat plane: and a heatsink member comprising a plate portion which is soldered to the flat plane of the metal cap and the semiconductor element to complete a hermetic sealing of the semiconductor element.

公开(公告)号：US5065223A

公开(公告)日：1991-11-12

申请号：US531457

申请日：1990-05-31

申请人： Hirohisa Matsuki ,  Shigeki Harada ,  Masahiro Sugimoto ,  Toshiki Yoshida

发明人： Hirohisa Matsuki ,  Shigeki Harada ,  Masahiro Sugimoto ,  Toshiki Yoshida

IPC分类号： H01L23/055 ,  H01L23/367 ,  H01L23/498

CPC分类号： H01L23/3675 ,  H01L23/055 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/01079

摘要： A semiconductor device includes a semiconductor chip, a substrate for supporting the semiconductor chip, a plurality of terminals provided on the substrate for external connections, a plurality of lead wires provided on the semiconductor chip for connections to the terminals, and a multilevel interconnection structure for connecting the plurality of terminals to the plurality of lead wires on the semiconductor chip. The multilevel interconnection structure includes at least a lower conductor layer provided on the substrate and patterned into a plurality of pattern portions connected electrically to the terminals, an insulator layer provided on the lower conductor layer, and an upper conductor layer provided above the insulator layer. The upper conductor layer is formed with a connection area immediately below the lead wires on the semiconductor chip when the semiconductor chip is mounted on the substrate, the upper conductor layer is patterned in the connection area into a plurality of conductor strips extending parallel with each other in correspondence to the lead wires, the insulator layer is provided with contact holes so as to connect electrically the conductor strips of the upper conductor layer with the pattern portions of the lower conductor layer. In the semiconductor device, each of the pattern portions in the connection area has an edge extending obliquely to the conductor strips of the upper conductor layer wherein the pattern portions are disposed so that a pair of adjacent pattern portions have respective edges opposing with each other and extending parallel with each other with a lateral gap extending therebetween.