公开(公告)号：US20140191334A1

公开(公告)日：2014-07-10

申请号：US13734201

申请日：2013-01-04

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

IPC分类号： H01L23/495 ,  H01L27/088

CPC分类号： H01L23/49575 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L27/088 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

摘要翻译： 叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。 在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。 安装夹在第一半导体芯片的背面连接到电极。 第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。

公开(公告)号：US08722466B2

公开(公告)日：2014-05-13

申请号：US12722528

申请日：2010-03-12

申请人： Jun Lu ,  Kai Liu ,  Yan Xun Xue

发明人： Jun Lu ,  Kai Liu ,  Yan Xun Xue

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/565 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L25/07 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

摘要翻译： 具有用于内部连接的连接板的半导体封装包括：多个芯片，每个芯片在顶表面上具有多个接触区域; 一个或多个连接板具有多个电隔离的连接板部分，每个连接板部分连接半导体芯片的接触区域。 制造半导体封装的方法包括将一个或多个连接板连接到多个半导体芯片的步骤，施加模制材料以封装芯片和连接板，将连接板的多个连接板部分分开浅 切割或磨削。

公开(公告)号：US20140114089A1

公开(公告)日：2014-04-24

申请号：US14055054

申请日：2013-10-16

申请人： Weitong DONG ,  Christian Wolfgang Hemp ,  Xiangle Jin ,  Jun Lu ,  Ulrich Scholz ,  Shengmin Su ,  Wei Xu ,  Jinsong Yang

发明人： Weitong DONG ,  Christian Wolfgang Hemp ,  Xiangle Jin ,  Jun Lu ,  Ulrich Scholz ,  Shengmin Su ,  Wei Xu ,  Jinsong Yang

IPC分类号： C07C249/02

CPC分类号： C07C213/00 ,  C07C217/76 ,  C07C249/02 ,  C07C257/08 ,  C07C257/18

摘要： The present invention relates to a process for the preparation of 4-aminobenzoamidine (4-AMBA) salts of general formula (I) preferably the salts thereof with hydrochloric or hydrobromic acid, particularly preferred the dichloride salt.

摘要翻译： 本发明涉及制备通式（I）的4-氨基苯甲脒（4-AMBA）盐的方法，优选其盐与盐酸或氢溴酸，特别优选二氯化物盐。

公开(公告)号：US08581376B2

公开(公告)日：2013-11-12

申请号：US12819111

申请日：2010-06-18

申请人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

发明人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

IPC分类号： H01L21/44 ,  H01L21/31

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

摘要翻译： 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。

公开(公告)号：US20130221507A1

公开(公告)日：2013-08-29

申请号：US13408185

申请日：2012-02-29

申请人： Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

发明人： Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.

摘要翻译： 半导体封装设置有没有贵金属的铝合金引线框架，镀在铝基底引线框架上。 提供具有适当的合金组成和制造铝合金引线框架的比例的铝合金材料。 铝合金引线框架依次电镀有第一金属电镀层，第二电镀层和第三电镀层。 然后，利用第一，第二和第三金属电镀层电镀的引线框架用于包括芯片连接，引线接合和塑性模制的功率半导体封装的制造过程中。 在模制过程之后，未被模塑料覆盖的引线框架的区域用暴露于空气中不容易氧化的第四金属电镀层电镀。

公开(公告)号：US08481368B2

公开(公告)日：2013-07-09

申请号：US13092059

申请日：2011-04-21

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L21/44

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/13099 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32506 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73153 ,  H01L2224/73255 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

摘要翻译： 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

公开(公告)号：US20130006927A1

公开(公告)日：2013-01-03

申请号：US13615138

申请日：2012-09-13

申请人： Brian Brockway ,  Parag Gokhale ,  Jun Lu

发明人： Brian Brockway ,  Parag Gokhale ,  Jun Lu

IPC分类号： G06F17/30

CPC分类号： G06F17/30309 ,  G06F7/00 ,  G06F11/14 ,  G06F11/1448 ,  G11C2029/0409 ,  Y10S707/99955

摘要： A system and method are provided for verifying data copies and reverifying the copies over the life span of media according to a verification policy. Characteristics of media and use of media are tracked to provide metrics which may be used to dynamically reevaluate and reassign verification policies to optimize media usage. Copies that fail verification operations may be repaired by repeating a storage operation for recent copies or by substituting a close temporal copy of the failed copy.

摘要翻译： 提供了一种系统和方法，用于根据验证策略验证数据副本并在媒体的使用寿命内重新验证副本。 跟踪媒体的特点和媒体的使用情况，提供可用于动态重新评估和重新分配验证策略以优化媒体使用情况的指标。 可以通过对最近的副本重复存储操作或通过替换失败副本的紧密暂时副本来修复失败验证操作的副本。

公开(公告)号：US20120255409A1

公开(公告)日：2012-10-11

申请号：US13518023

申请日：2010-12-23

申请人： Aimin Deng ,  Hui Ding ,  Jun Lu ,  Jianrong Xie

发明人： Aimin Deng ,  Hui Ding ,  Jun Lu ,  Jianrong Xie

IPC分类号： C25C7/08

CPC分类号： C25C7/08 ,  Y10T83/2185 ,  Y10T83/2187 ,  Y10T83/219

摘要： An apparatus for stripping metal sheets from a cathode blank comprises: a frame; a stripping assembly disposed on the frame; and a receiving mechanism comprising at least one receiving platform which is disposed on the frame for receiving the deposited metal sheets. The stripping assembly comprises: at least one clipping mechanism for clipping a conductive member on an upper end of the cathode blank; first and second stripping mechanisms for stripping the deposited metal sheets from two surfaces of the cathode blank; a bottom positioning mechanism for positioning a lower end of the cathode blank; and first and second loosening mechanisms each comprising a push rod which is movably disposed on the frame in the transversal direction for pushing the cathode blank.

摘要翻译： 用于从阴极坯料剥离金属片的设备包括：框架; 设置在框架上的剥离组件; 以及接收机构，其包括至少一个接收平台，所述接收平台设置在所述框架上用于接收沉积的金属片。 剥离组件包括：至少一个夹持机构，用于夹住阴极坯料的上端上的导电构件; 用于从阴极坯料的两个表面剥离沉积的金属片的第一和第二剥离机构; 用于定位阴极毛坯的下端的底部定位机构; 以及第一和第二松动机构，每个包括推杆，该推杆在横向上可移动地设置在框架上以推动阴极坯料。

公开(公告)号：US08217503B2

公开(公告)日：2012-07-10

申请号：US12881372

申请日：2010-09-14

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/84

摘要： A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

摘要翻译： 本文公开的用于DC-DC转换器的封装结构可以减少封装元件的数量，因为低侧MOSFET芯片可以堆叠在第一裸片焊盘的高侧MOSFET芯片上方，通过具有不同厚度的芯片焊盘或具有接头的插入件 不同厚度的零件; 而且，由于控制器和低侧MOSFET芯片之间的空间中包含多个接合线，因此进一步减小了整个半导体封装的尺寸。 此外，利用金属接合板实现了顶部源极电极引脚和低端MOSFET芯片的底部源极电极引脚之间的电连接，使得当DC-DC转换器用塑料密封时，金属接合板可以 暴露在外面以改善热性能并有效地减小半导体封装的厚度。

公开(公告)号：US20120161304A1

公开(公告)日：2012-06-28

申请号：US13411990

申请日：2012-03-05

申请人： Kai Liu ,  Lei Shi ,  Jun Lu ,  Anup Bhalla

发明人： Kai Liu ,  Lei Shi ,  Jun Lu ,  Anup Bhalla

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/24247 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/92246 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

摘要翻译： 双引线框多芯片封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘的第二引线框架; 安装在用作高边MOSFET的第一芯片焊盘上的第一芯片和安装在用作低端MOSFET的第二芯片焊盘上的第二芯片。 封装还可以包括配置为安装在第一裸片焊盘上或与第一芯片集成的第三芯片的旁路容量。 封装还可以包括形成为一体结构的三维连接板作为第二芯片焊盘，用于将第一芯片的顶部接触区域电连接到第二芯片的底部接触区域。 顶部连接板将第二芯片的顶部接触区域和第三芯片的顶部接触区域连接到第一引线框架的外部引脚。