公开(公告)号：US08703545B2

公开(公告)日：2014-04-22

申请号：US13408185

申请日：2012-02-29

申请人： Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

发明人： Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

IPC分类号： H01L21/56 ,  H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.

摘要翻译： 半导体封装设置有没有贵金属的铝合金引线框架，镀在铝基底引线框架上。 提供具有适当的合金组成和制造铝合金引线框架的比例的铝合金材料。 铝合金引线框架依次电镀有第一金属电镀层，第二电镀层和第三电镀层。 然后，利用第一，第二和第三金属电镀层电镀的引线框架用于包括芯片连接，引线接合和塑性模制的功率半导体封装的制造过程中。 在模制过程之后，未被模塑料覆盖的引线框架的区域用暴露于空气中不容易氧化的第四金属电镀层电镀。

公开(公告)号：US20130221507A1

公开(公告)日：2013-08-29

申请号：US13408185

申请日：2012-02-29

申请人： Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

发明人： Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.

摘要翻译： 半导体封装设置有没有贵金属的铝合金引线框架，镀在铝基底引线框架上。 提供具有适当的合金组成和制造铝合金引线框架的比例的铝合金材料。 铝合金引线框架依次电镀有第一金属电镀层，第二电镀层和第三电镀层。 然后，利用第一，第二和第三金属电镀层电镀的引线框架用于包括芯片连接，引线接合和塑性模制的功率半导体封装的制造过程中。 在模制过程之后，未被模塑料覆盖的引线框架的区域用暴露于空气中不容易氧化的第四金属电镀层电镀。

公开(公告)号：US20140175628A1

公开(公告)日：2014-06-26

申请号：US13724006

申请日：2012-12-21

申请人： Hua Pan ,  Yueh-Se Ho ,  Jun Lu ,  Ming-Chen Lu ,  Zhiqiang Niu

发明人： Hua Pan ,  Yueh-Se Ho ,  Jun Lu ,  Ming-Chen Lu ,  Zhiqiang Niu

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L24/97 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40479 ,  H01L2224/4048 ,  H01L2224/40499 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48647 ,  H01L2224/48847 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8491 ,  H01L2224/92 ,  H01L2224/92142 ,  H01L2224/92147 ,  H01L2224/92157 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92246 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/386 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/01079 ,  H01L2224/03 ,  H01L21/78 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/2075 ,  H01L2924/20754 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A semiconductor device comprises a first top electrode and a second top electrode at a front surface of the die, at least a Ni plating layer and an Au plating layer overlaying the Ni plating layer are formed on each of the first top electrode and the second top electrode. A copper clip attaches on the Au plating layer of the second top electrode. A gold (Au) stud bump is formed on the Au plating layer of the first top electrode with a copper wire connected on the stud bump. The Au stud bump is thicker than a thickness of the Au plating layer and thinner than a thickness of the copper clip to avoid copper wire NSOP (non-stick on pad) problem due to Ni plating layer diffusion during the solder reflow process in the copper clip attachment.

摘要翻译： 半导体器件包括在管芯的前表面处的第一顶电极和第二顶电极，在第一顶电极和第二顶部的每一个上形成至少Ni镀层和覆盖Ni镀层的Au镀层 电极。 铜夹附着在第二顶电极的Au镀层上。 在第一顶电极的Au镀层上形成金（Au）柱凸块，铜柱连接在凸块上。 Au凸块比Au镀层的厚度厚，比铜夹的厚度薄，以避免在铜回焊过程中镀镍层扩散的铜线NSOP（不粘垫）问题 夹子附件。

公开(公告)号：US09006870B2

公开(公告)日：2015-04-14

申请号：US13955206

申请日：2013-07-31

申请人： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

发明人： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

IPC分类号： H01L23/34 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/07 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/118 ,  H01L2224/13022 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

摘要翻译： 堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和 第三个半导体芯片堆叠在餐夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。

公开(公告)号：US20150035129A1

公开(公告)日：2015-02-05

申请号：US13955206

申请日：2013-07-31

申请人： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

发明人： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/07 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/118 ,  H01L2224/13022 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

摘要翻译： 堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和 第三个半导体芯片堆叠在餐夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。

公开(公告)号：US20080012106A1

公开(公告)日：2008-01-17

申请号：US11530178

申请日：2006-09-08

申请人： Hua Pan ,  Jie-Hung Chiou ,  Chih-Lung Huang

发明人： Hua Pan ,  Jie-Hung Chiou ,  Chih-Lung Huang

IPC分类号： H01L23/02

CPC分类号： H01L23/4951 ,  H01L23/13 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface and chip bonding pads disposed thereon. The lead frame is fixed on the chip and the lead frame includes inner leads, at least one bus bar, an insulating layer and transfer bonding pads. The bus bar is located between the chip bonding pads and the inner leads. The insulating layer is disposed on the bus bar and the transfer bonding pads are disposed thereon. The inner leads and the bus bar are located above the active surface. The chip and the insulating layer are located respectively on two opposite surfaces of the bus bar. The first bonding wires respectively connect the chip bonding pads and the transfer bonding pads. The second bonding wires respectively connect the transfer bonding pads and the inner leads.

摘要翻译： 提供了包括芯片，引线框架，第一接合线和第二接合线的芯片封装结构。 芯片具有设置在其上的有源表面和芯片接合焊盘。 引线框架固定在芯片上，引线框架包括内引线，至少一个汇流条，绝缘层和转移键合垫。 母线位于芯片焊盘和内引线之间。 绝缘层设置在母线上，并且转移接合焊盘设置在母线上。 内引线和母线位于有源表面上方。 芯片和绝缘层分别位于母线的两个相对的表面上。 第一接合线分别连接芯片接合焊盘和转移接合焊盘。 第二接合线分别连接转移接合焊盘和内部引线。

公开(公告)号：US08617516B2

公开(公告)日：2013-12-31

申请号：US12910385

申请日：2010-10-22

申请人： Samuel A. Wickline ,  Hua Pan ,  Neelesh R. Soman ,  Gregory M. Lanza ,  Paul H. Schlesinger

发明人： Samuel A. Wickline ,  Hua Pan ,  Neelesh R. Soman ,  Gregory M. Lanza ,  Paul H. Schlesinger

IPC分类号： A61K51/00 ,  A61M36/14

CPC分类号： A61K9/5123 ,  A61K49/1806

摘要： The present invention provides a substantially non-lytic, non-cytotoxic anchor peptide that is capable of stably inserting into lipid membranes. In particular, the invention provides nanoparticles comprising stably inserted anchor peptides, which may be conjugated to a variety of different cargo complexes.

摘要翻译： 本发明提供了能够稳定地插入脂质膜中的基本上非裂解性的非细胞毒性锚定肽。 特别地，本发明提供包含稳定插入的锚定肽的纳米颗粒，其可以缀合到各种不同的货物配合物。

公开(公告)号：US20110123438A1

公开(公告)日：2011-05-26

申请号：US12910385

申请日：2010-10-22

申请人： Samuel A. Wickline ,  Hua Pan ,  Neelesh R. Soman ,  Gregory M. Lanza ,  Paul H. Schlesinger

发明人： Samuel A. Wickline ,  Hua Pan ,  Neelesh R. Soman ,  Gregory M. Lanza ,  Paul H. Schlesinger

IPC分类号： A61K51/12 ,  A61K9/14 ,  A61K49/18 ,  A61K49/22 ,  A61K39/00 ,  A61P43/00

CPC分类号： A61K9/5123 ,  A61K49/1806

摘要： The present invention provides a substantially non-lytic, non-cytotoxic anchor peptide that is capable of stably inserting into lipid membranes. In particular, the invention provides nanoparticles comprising stably inserted anchor peptides, which may be conjugated to a variety of different cargo complexes.

摘要翻译： 本发明提供了能够稳定地插入脂质膜中的基本上非裂解性的非细胞毒性锚定肽。 特别地，本发明提供包含稳定插入的锚定肽的纳米颗粒，其可以缀合到各种不同的货物配合物。

公开(公告)号：US08039946B2

公开(公告)日：2011-10-18

申请号：US12630103

申请日：2009-12-03

申请人： Hua Pan ,  Jie-Hung Chiou ,  Chih-Lung Huang

发明人： Hua Pan ,  Jie-Hung Chiou ,  Chih-Lung Huang

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/4951 ,  H01L23/13 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface and chip bonding pads disposed thereon. The lead frame is fixed on the chip and the lead frame includes inner leads, at least one bus bar, an insulating layer and transfer bonding pads. The bus bar is located between the chip bonding pads and the inner leads. The insulating layer is disposed on the bus bar and the transfer bonding pads are disposed thereon. The inner leads and the bus bar are located above the active surface. The chip and the insulating layer are located respectively on two opposite surfaces of the bus bar. The first bonding wires respectively connect the chip bonding pads and the transfer bonding pads. The second bonding wires respectively connect the transfer bonding pads and the inner leads.

摘要翻译： 提供了包括芯片，引线框架，第一接合线和第二接合线的芯片封装结构。 芯片具有设置在其上的有源表面和芯片接合焊盘。 引线框架固定在芯片上，引线框架包括内引线，至少一个汇流条，绝缘层和转移键合垫。 母线位于芯片焊盘和内引线之间。 绝缘层设置在母线上，并且转移接合焊盘设置在母线上。 内引线和母线位于有源表面上方。 芯片和绝缘层分别位于母线的两个相对的表面上。 第一接合线分别连接芯片接合焊盘和转移接合焊盘。 第二接合线分别连接转移接合焊盘和内部引线。

公开(公告)号：US20100078802A1

公开(公告)日：2010-04-01

申请号：US12630103

申请日：2009-12-03

申请人： Hua Pan ,  Jie-Hung Chiou ,  Chih-Lung Huang

发明人： Hua Pan ,  Jie-Hung Chiou ,  Chih-Lung Huang

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/4951 ,  H01L23/13 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface and chip bonding pads disposed thereon. The lead frame is fixed on the chip and the lead frame includes inner leads, at least one bus bar, an insulating layer and transfer bonding pads. The bus bar is located between the chip bonding pads and the inner leads. The insulating layer is disposed on the bus bar and the transfer bonding pads are disposed thereon. The inner leads and the bus bar are located above the active surface. The chip and the insulating layer are located respectively on two opposite surfaces of the bus bar. The first bonding wires respectively connect the chip bonding pads and the transfer bonding pads. The second bonding wires respectively connect the transfer bonding pads and the inner leads.