公开(公告)号：US07630233B2

公开(公告)日：2009-12-08

申请号：US10593576

申请日：2005-03-30

申请人： Kiyoshi Kato ,  Yasuyuki Arai ,  Shunpei Yamazaki

发明人： Kiyoshi Kato ,  Yasuyuki Arai ,  Shunpei Yamazaki

IPC分类号： G11C11/00

CPC分类号： G06K19/0723 ,  G11C13/0004 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144

摘要： The invention provides a semiconductor device including a memory of a simple structure to provide an inexpensive semiconductor device and a driving method thereof. The semiconductor device of the invention includes a phase change memory including a memory cell array having a plurality of memory cells, a control circuit that controls the phase change memory, and an antenna. The memory cell array includes a plurality of bit lines that extend in a first direction and word lines that extend in a second direction perpendicular to the first direction. Each of the plurality of memory cells includes a phase change layer provided between the bit lines and the word lines. In the semiconductor device having the aforementioned structure, one or both of a conductive layer that forms the bit lines and a conductive layer that forms the word lines transmits light.

摘要翻译： 本发明提供一种包括简单结构的存储器以提供便宜的半导体器件及其驱动方法的半导体器件。 本发明的半导体器件包括：相变存储器，包括具有多个存储单元的存储单元阵列，控制相变存储器的控制电路和天线。 存储单元阵列包括沿第一方向延伸的多个位线和在垂直于第一方向的第二方向上延伸的字线。 多个存储单元中的每一个包括设置在位线和字线之间的相变层。 在具有上述结构的半导体器件中，形成位线的导电层和形成字线的导电层中的一个或两个透射光。

公开(公告)号：US07375376B2

公开(公告)日：2008-05-20

申请号：US11633579

申请日：2006-12-05

申请人： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame ,  Takashi Hirosue ,  Saishi Fujikawa

发明人： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame ,  Takashi Hirosue ,  Saishi Fujikawa

IPC分类号： H01L29/786 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/1244 ,  G02F1/136204 ,  H01L21/76804 ,  H01L21/76831 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3244 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78645 ,  H01L51/0037 ,  Y10S257/906 ,  Y10S257/908

摘要： A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

摘要翻译： 具有层间绝缘膜的半导体显示装置，其中以有限的成膜时间确保表面水平度，除去水分的热处理不需要很长时间，并且防止层间绝缘膜中的水分逸出到邻近的膜或电极 层间绝缘膜。 形成TFT，然后形成与有机树脂膜相比传递较少水分的含氮无机绝缘膜，以覆盖TFT。 接下来，施加包含感光性丙烯酸树脂的有机树脂，并通过将有机树脂膜部分地曝光而形成开口。 然后，形成有开口部的有机树脂膜被覆盖有比有机树脂膜透过少的水分的含氮无机绝缘膜。 此后，在有机树脂膜的开口部分将栅极绝缘膜和含氮无机绝缘膜的两层部分地蚀刻掉，以暴露TFT的有源层。

公开(公告)号：US20080049500A1

公开(公告)日：2008-02-28

申请号：US11776973

申请日：2007-07-12

申请人： Kiyoshi Kato ,  Shunpei Yamazaki

发明人： Kiyoshi Kato ,  Shunpei Yamazaki

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/0458 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/12 ,  H01L27/124

摘要： A highly-integrated nonvolatile memory. A memory cell array where plural memory cells are arranged in matrix in row and column directions, plural first and second word lines, and plural bit lines are included. Each of the plural memory cells includes a first memory transistor and a second memory transistor which are connected in series. A gate electrode of the first memory transistor is connected to the first word line, a gate electrode of the second memory transistor is connected to the second word line, one of source and drain regions of the first memory transistor is connected to the first bit line, and one of source and drain regions of the second memory transistor is connected to the second bit line. Each of the first bit line and the second bit line is provided in common for memory cells in columns which are adjacent to each other.

摘要翻译： 高度集成的非易失性存储器。 存储单元阵列，其中多个存储单元以行和列方向排列成矩阵，多个第一和第二字线以及多个位线。 多个存储单元中的每一个包括串联连接的第一存储晶体管和第二存储晶体管。 第一存储晶体管的栅电极连接到第一字线，第二存储晶体管的栅电极连接到第二字线，第一存储晶体管的源极和漏极区之一连接到第一位线 并且第二存储晶体管的源极和漏极区中的一个连接到第二位线。 第一位线和第二位线中的每一个被共同地设置在彼此相邻的列中的存储器单元。

公开(公告)号：US20050146006A1

公开(公告)日：2005-07-07

申请号：US11018151

申请日：2004-12-22

申请人： Shunpei Yamazaki ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Kiyoshi Kato

IPC分类号： G06K19/06 ,  G06K19/077 ,  G07D7/00 ,  H01L23/02 ,  H01L23/498

CPC分类号： H01L23/49855 ,  G06K19/07749 ,  G06K19/07758 ,  G06K19/07767 ,  G07D7/01 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In view of the foregoing, an integrated circuit having a semiconductor film with a thickness of 0.2 μm or less is mounted on securities including bills, belongings, containers of food and drink, and the like (hereinafter referred to as products and the like). The ID chip of the invention can be reduced in cost and increased in impact resistance as compared with a chip formed over a silicon wafer while maintaining an attractive design.

摘要翻译： 本发明提供一种具有降低成本，增加耐冲击性和有吸引力的设计的ID芯片以及安装ID芯片的产品等及其制造方法。 鉴于上述，将厚度为0.2μm以下的半导体膜的集成电路安装在包括纸币，财物，食品和饮料容器等的证券（以下称为产品等）上。 与保持有吸引力的设计的硅晶片上形成的芯片相比，本发明的ID芯片可以降低成本并增加耐冲击性。

公开(公告)号：US06812491B2

公开(公告)日：2004-11-02

申请号：US10393768

申请日：2003-03-21

申请人： Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Shunpei Yamazaki

发明人： Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Shunpei Yamazaki

IPC分类号： H01L2976

CPC分类号： H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/04 ,  H01L29/42332 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792

摘要： An insulating film with a linear concave portion is formed and a semiconductor film is formed thereon by deposition. The semiconductor film is irradiated with laser light to melt the semiconductor film and the melted semiconductor is poured into the concave portion, where it is crystallized. This makes distortion or stress accompanying crystallization concentrate on other regions than the concave portion. A surface of this crystalline semiconductor film is etched away, thereby forming in the concave portion a crystalline semiconductor film which is covered with side walls of the concave portion from the sides and which has no other grain boundaries than twin crystal. TFTs and memory TFTs having this crystalline semiconductor film as their channel regions are highly reliable, have high field effect mobility, and are less fluctuated in characteristic. Accordingly, a highly reliable semiconductor memory device which can operate at high speed is obtained.

公开(公告)号：US08698219B2

公开(公告)日：2014-04-15

申请号：US13004200

申请日：2011-01-11

申请人： Yusuke Sekine ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Shunpei Yamazaki

发明人： Yusuke Sekine ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

摘要： A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state (off-state current) between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or to the memory cell by applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another so that the predetermined amount of charge is held in the node. The memory window width is changed by 2% or less, before and after 1×109 times of writing.

摘要翻译： 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态（截止状态电流）中具有小的漏电流，读取晶体管包括不同于 写晶体管和电容器。 通过向写入晶体管的源电极和漏电极，电容器的一个电极和读取晶体管的栅电极之一彼此电连接的节点施加电位而将数据写入或存储到存储器单元，从而 在节点中保持预定量的电荷。 1×109次写入之前和之后，存储窗宽度改变2％以下。

公开(公告)号：US08649201B2

公开(公告)日：2014-02-11

申请号：US11883027

申请日：2006-01-24

申请人： Kiyoshi Kato ,  Konami Izumi ,  Shunpei Yamazaki

发明人： Kiyoshi Kato ,  Konami Izumi ,  Shunpei Yamazaki

IPC分类号： G11C17/00

CPC分类号： H01L27/1255 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/53 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/285 ,  H01L51/0059

摘要： To provide a memory device which operates with low power consumption, has high reliability of the stored data, and is small-size, light-weight and inexpensive, and a driving method thereof. In addition, to provide a semiconductor device which operates with low power consumption, has high reliability of the stored data and a long distance of radio frequency communication, and is small-size, light-weight and inexpensive, and a driving method thereof. The memory device includes a memory cell array in which at least memory elements are arranged in matrix, and a writing circuit. The memory element has a first conductive layer, a second conductive layer, and an organic compound layer formed therebetween, and the writing circuit includes a voltage generating circuit for generating a voltage in order to apply at plural times, and a timing controlling circuit for controlling output time of the voltage.

摘要翻译： 为了提供以低功耗工作的存储器件，具有高可靠性的存储数据，并且体积小，重量轻且便宜，并且其驱动方法。 此外，为了提供以低功耗工作的半导体装置，具有高可靠性的存储数据和长距离的射频通信，并且体积小，重量轻且便宜，以及其驱动方法。 存储器件包括至少存储器元件排列成矩阵的存储单元阵列和写入电路。 存储元件具有形成在其间的第一导电层，第二导电层和有机化合物层，并且写入电路包括用于产生电压以便多次施加的电压产生电路，以及用于控制的定时控制电路 电压的输出时间。

公开(公告)号：US08008666B2

公开(公告)日：2011-08-30

申请号：US12711611

申请日：2010-02-24

申请人： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame

发明人： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame

IPC分类号： H01L29/04

CPC分类号： H01L27/1248 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3246 ,  H01L27/3276 ,  H01L33/52 ,  H01L51/5237 ,  H01L51/5253

摘要： It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

摘要翻译： 本发明的目的是提供一种具有层间绝缘膜的半导体显示装置，其可以在控制成膜时间的同时获得表面的平面性，并且可以控制用于除去水分的加热处理的处理时间，并且可以防止水分 在层间绝缘膜中不被放电到与层间绝缘膜相邻的膜或电极。 形成与有机树脂相比不容易透过水分的含氮的无机绝缘膜，以覆盖TFT。 接着，在有机绝缘膜上涂布含有感光性丙烯酸树脂的有机树脂膜，将有机树脂膜部分地曝光以打开。 然后，形成与有机树脂相比不容易透过水分的含有氮的无机绝缘膜，以覆盖打开的有机树脂膜。 然后，在有机树脂膜的开口部分中，通过蚀刻部分地打开栅极绝缘膜和含氮的两层无机绝缘膜，以暴露TFT的有源层。

公开(公告)号：US07857229B2

公开(公告)日：2010-12-28

申请号：US12486838

申请日：2009-06-18

申请人： Shunpei Yamazaki ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Kiyoshi Kato

IPC分类号： G06K19/06

CPC分类号： H01L23/49855 ,  G06K19/07749 ,  G06K19/07758 ,  G06K19/07767 ,  G07D7/01 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In view of the foregoing, an integrated circuit having a semiconductor film with a thickness of 0.2 μm or less is mounted on securities including bills, belongings, containers of food and drink, and the like (hereinafter referred to as products and the like). The ID chip of the invention can be reduced in cost and increased in impact resistance as compared with a chip formed over a silicon wafer while maintaining an attractive design.

摘要翻译： 本发明提供一种具有降低成本，增加耐冲击性和有吸引力的设计的ID芯片以及安装ID芯片的产品等及其制造方法。 鉴于上述，将厚度为0.2μm以下的半导体膜的集成电路安装在包括纸币，财物，食品和饮料容器等的证券（以下称为产品等）上。 与保持有吸引力的设计的硅晶片上形成的芯片相比，本发明的ID芯片可以降低成本并增加耐冲击性。

公开(公告)号：US07671369B2

公开(公告)日：2010-03-02

申请号：US10400427

申请日：2003-03-28

申请人： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame

发明人： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame

IPC分类号： H01L29/04

CPC分类号： H01L27/1248 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3246 ,  H01L27/3276 ,  H01L33/52 ,  H01L51/5237 ,  H01L51/5253

摘要： It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

摘要翻译： 本发明的目的是提供一种具有层间绝缘膜的半导体显示装置，其可以在控制成膜时间的同时获得表面的平面性，并且可以控制加热处理的处理时间，同时除去水分，并且可以防止水分 在层间绝缘膜中不被放电到与层间绝缘膜相邻的膜或电极。 形成与有机树脂相比不容易透过水分的含氮的无机绝缘膜，以覆盖TFT。 接着，在有机绝缘膜上涂布含有感光性丙烯酸树脂的有机树脂膜，将有机树脂膜部分地曝光以打开。 然后，形成与有机树脂相比不容易透过水分的含有氮的无机绝缘膜，以覆盖打开的有机树脂膜。 然后，在有机树脂膜的开口部分中，通过蚀刻部分地打开栅极绝缘膜和含氮的两层无机绝缘膜，以暴露TFT的有源层。