公开(公告)号：US20170148511A1

公开(公告)日：2017-05-25

申请号：US15426070

申请日：2017-02-07

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hsiao-Te Chang ,  Wen-Long Wang

IPC: G11C11/56 ,  G11C16/08 ,  G06F3/06

CPC classification number: G11C11/5642 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/26

Abstract: A memory access module for performing memory access management of a storage device including a plurality of storage cells includes: sensing means for performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages in order to generate a first digital value and a second digital value of a storage cell; processing means for using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; decoding means for using the soft information to perform soft decoding; and controlling means for accessing the storage device. The controlling means includes: storage means for storing a program code; and processing means for executing a program code to control access to the storage device and manage the plurality of storage cells.

公开(公告)号：US20170046225A1

公开(公告)日：2017-02-16

申请号：US15232814

申请日：2016-08-10

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G06F3/06 ,  G11C16/26 ,  G11C29/52 ,  G11C11/56 ,  G11C16/10

CPC classification number: G06F11/1072 ,  G06F11/1068 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A method for accessing a flash memory module includes: sequentially writing Nth-(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth-(N+K)th data to generate Nth-(N+K)th ECCs, respectively, where the Nth-(N+K) th ECCs are used to correct errors of the Nth-(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth-(N+K)th ECCs to generate the (N+K+1)th ECC.

Abstract translation: 一种用于访问闪存模块的方法包括：将第N（N + K）个数据顺序地写入闪存模块的多个闪速存储器芯片，并对第N（N + K）个数据进行编码以产生第N- （N + K）个ECC，其中第N（N + K）个ECC分别用于校正第N（N + K）个数据的误差，N和K是正整数; 以及将所述第（N + K + 1）数据写入所述闪存模块的所述多个闪速存储器芯片，并且将所述第（N + K + 1）数据与所述第（N + 以产生（N + K + 1）ECC。

公开(公告)号：US09411686B2

公开(公告)日：2016-08-09

申请号：US14331591

申请日：2014-07-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/108 ,  G06F11/1012 ,  G06F2211/109

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit.

Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在RAID（独立磁盘冗余阵列）组中的所有消息被编程之后，确定是否已经生成RAID组内的垂直ECC（纠错码）。 处理单元引导DMA（直接存储器访问）控制器从DRAM（动态随机存取存储器）获得垂直ECC，并且当生成RAID组内的垂直ECC时，将垂直ECC存储到缓冲器，从而使垂直 ECC被编程到存储单元。

公开(公告)号：US20160093371A1

公开(公告)日：2016-03-31

申请号：US14956410

申请日：2015-12-02

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hsiao-Te Chang ,  Wen-Long Wang

IPC: G11C11/56 ,  G11C16/08

CPC classification number: G11C11/5642 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/26

Abstract: A method for performing memory access includes: performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages to generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value and the second digital value to obtain soft information of a bit stored in the Flash cell; and using the soft information to perform soft decoding.

Abstract translation: 一种用于执行存储器访问的方法包括：执行分别对应于多个不同感测电压的多个感测操作，以产生闪存的闪存单元的第一数字值和闪存的闪存单元的第二数字值 ; 使用第一数字值和第二数字值来获得存储在闪存单元中的位的软信息; 并使用软信息进行软解码。

公开(公告)号：US09293203B2

公开(公告)日：2016-03-22

申请号：US14171207

申请日：2014-02-03

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C19/04 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/16

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/3431

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract translation: 一种用于读取存储在闪速存储器中的数据的方法。 闪速存储器包括多个存储单元，并且每个存储单元具有特定的阈值电压。 该方法包括：获得表示第一组存储器单元的阈值电压的第一阈值电压分布; 获得表示第二组存储器单元的阈值电压的第二阈值电压分布，其中第二阈值电压分布与第一阈值电压分布不同，并且第一组存储器单元包括第二组的至少一部分 的记忆细胞; 以及控制所述闪速存储器，以根据所述第二阈值电压分布对所述第一组存储器单元执行至少一次读取操作。

公开(公告)号：US09256529B2

公开(公告)日：2016-02-09

申请号：US14596236

申请日：2015-01-14

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C16/04 ,  G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US20150301888A1

公开(公告)日：2015-10-22

申请号：US14666316

申请日：2015-03-24

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1102

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract translation: 用于读取存储在闪速存储器中的数据的示例性方法包括：从多个预定栅极电压组合选项中选择初始栅极电压组合; 根据初始栅极电压组合控制闪速存储器中的多个存储器单元，以及读取多个位序列; 对所述多个比特序列执行码字纠错，并确定所述码字错误校正是否成功; 如果码字纠错不成功，则确定电荷分布参数; 通过使用查找表来确定对应于电荷分布参数的目标栅极电压组合; 以及根据目标栅极电压组合来控制多个存储器单元读取多个更新的位序列。

公开(公告)号：US20150058662A1

公开(公告)日：2015-02-26

申请号：US14331575

申请日：2014-07-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G06F11/10 ,  G06F12/02 ,  G11C29/52

CPC classification number: G06F11/108 ,  G06F3/06 ,  G06F12/0246 ,  G11C2029/0411

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, includes at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

Abstract translation: 用于访问由仲裁器执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在第一批中将数据发送到连接到存储单元访问接口中的一个的第一存储单元之后，仲裁器向每个第一存储单元发出数据写入命令，从而使得每个第一存储单元能够启动物理数据编程。 在每个第一存储单元的物理数据编程期间，数据被发送到第二存储单元，每个存储单元在第二批中连接到一个存储单元访问接口。

公开(公告)号：US20140241067A1

公开(公告)日：2014-08-28

申请号：US14277007

申请日：2014-05-13

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3427 ,  G11C29/52 ,  G11C2211/5644 ,  G11C2211/5648 ,  H03M13/152

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract translation: 用于读取存储在闪速存储器中的数据的方法至少包括以下步骤：控制闪速存储器对包括在闪速存储器中的多个存储器单元执行多个读取操作; 分别从存储单元获取多个位序列，其中读操作通过利用不同的控制栅极电压设置从存储单元读取预定位序的位; 以及根据比特序列的二进制数字分配特性来确定存储器单元的读出信息。

公开(公告)号：US20140026018A1

公开(公告)日：2014-01-23

申请号：US13943755

申请日：2013-07-16

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  ZHEN-U LIU

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1076 ,  G11B20/1833 ,  H03M13/27 ,  H03M13/29

Abstract: A method for reading data from a block of a flash memory is provided, where the block includes a plurality of pages and at least one parity page, each of the pages includes a plurality of sectors used for storing data and associated row parities, each of the sectors of the parity page is used to store a column parity. The method includes: reading data from a specific page of the pages; decoding the data of the specific page; and when a specific sector of the specific page fails to be decoded, sequentially reading all original data of the pages and the parity page, and performing error correction upon the specific sector according to at least a portion of the original data of the pages and the parity page corresponding to the specific sector.

Abstract translation: 提供了一种用于从闪速存储器块读取数据的方法，其中该块包括多个页面和至少一个奇偶校验页面，每个页面包括用于存储数据和相关联的行奇偶校验的多个扇区，每个扇区 奇偶校验页面的扇区用于存储列奇偶校验。 该方法包括：从页面的特定页面读取数据; 解码特定页面的数据; 并且当特定页面的特定扇区不能被解码时，顺序地读取页面和奇偶校验页面的所有原始数据，并且根据页面的原始数据的至少一部分和特定扇区执行错误校正，并且 对应于特定扇区的奇偶校验页。