公开(公告)号：US06259633B1

公开(公告)日：2001-07-10

申请号：US09422198

申请日：1999-10-19

申请人： Tien-Min Chen ,  Kazuhiro Kurihara ,  Takao Akaogi

发明人： Tien-Min Chen ,  Kazuhiro Kurihara ,  Takao Akaogi

IPC分类号： G11C700

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C16/26

摘要： A flash memory device is provided with a two stage sense amplifier. The two stage sense amplifier includes a sense pre-amplifier coupled to a sense output amplifier. The sense pre-amplifier amplifies a data signal from a memory bank. The sense output amplifier then differentially compares the output of the sense pre-amplifier with a reference signal. An embodiment with first and second memory banks is also provided that is capable of simultaneous operation.

摘要翻译： 闪存器件设置有两级读出放大器。 两级读出放大器包括耦合到感测输出放大器的感测预放大器。 感测前置放大器放大来自存储体的数据信号。 然后，感测输出放大器将感测预放大器的输出与参考信号进行差分比较。 还提供了具有第一和第二存储体的实施例，其能够同时操作。

公开(公告)号：US06240044B1

公开(公告)日：2001-05-29

申请号：US09467649

申请日：1999-12-20

申请人： Takao Akaogi

发明人： Takao Akaogi

IPC分类号： G11C800

CPC分类号： G11C16/32 ,  G11C8/04 ,  G11C16/08 ,  G11C16/30

摘要： A high speed address sequencer allows for a generation of address signals using a clock with higher frequency. The high speed address sequencer can be used in many semiconductor devices, especially in flash memory devices. By reducing a number of gate delays, the high speed address sequencer can generate all address signals in a reduced time period. By using an address signal as a clock for generation of some of the other address signals, the high speed address sequencer is allowed more time to generate all address signals with a given clock frequency. The reduction in the number of gate delays can be combined with the use of the address signal as a clock.

摘要翻译： 高速地址排序器允许使用更高频率的时钟产生地址信号。 高速地址定序器可用于许多半导体器件，特别是在闪存器件中。 通过减少多个门延迟，高速地址定序器可以在缩短的时间周期内产生所有地址信号。 通过使用地址信号作为生成其它一些地址信号的时钟，高速地址定序器被允许更多的时间来产生具有给定时钟频率的所有地址信号。 可以将门延迟数量的减少与使用地址信号作为时钟组合。

公开(公告)号：US06212108B1

公开(公告)日：2001-04-03

申请号：US09490340

申请日：2000-01-24

申请人： Takao Akaogi ,  Lee Edward Cleveland

发明人： Takao Akaogi ,  Lee Edward Cleveland

IPC分类号： G11C700

CPC分类号： G11C7/1048 ,  G11C11/4096

摘要： A memory device (100) includes a core cell array (102), a sense amplifier circuit (110), data lines (120), each having a length. The memory device further includes bit lines (118) extending from the core cell array and a selection circuit (106) configured to selectively couple a bit line to a data line in response to an input address. Bias circuits (130) are distributed along the length of the data lines and are configured to apply an initial voltage to the data line, reducing the read access time of the memory device. The bias circuits 130 may be positioned to accommodate varying lengths of the data lines and varying capacitance of the data lines.

摘要翻译： 存储器件（100）包括芯单元阵列（102），读出放大器电路（110），数据线（120），每个具有一个长度。 存储器件还包括从核心单元阵列延伸的位线（118）和配置为响应于输入地址选择性地将位线耦合到数据线的选择电路（106）。 偏置电路（130）沿着数据线的长度分布并且被配置为向数据线施加初始电压，从而减少存储器件的读取访问时间。 偏置电路130可以被定位成适应不同长度的数据线和数据线的变化电容。

公开(公告)号：US06201753B1

公开(公告)日：2001-03-13

申请号：US09421142

申请日：1999-10-19

申请人： Takao Akaogi ,  Kazuhiro Kurihara

发明人： Takao Akaogi ,  Kazuhiro Kurihara

IPC分类号： G11C700

CPC分类号： G11C15/00

摘要： A content addressable memory (CAM) circuit (200) is used as a data storage circuit to store information about operational mode and timing in a flash memory chip (100). To minimize current drain in a standby mode, the CAM circuit is placed in a low power state. To prevent unwanted switching of the output node (240) and eliminate excess current drain and mode switching of other circuits in the flash memory chip, the output of the CAM circuit is latched.

摘要翻译： 内容可寻址存储器（CAM）电路（200）用作数据存储电路，用于将有关操作模式和定时的信息存储在闪存芯片（100）中。 为了最小化待机模式下的电流消耗，CAM电路处于低功耗状态。 为了防止输出节点（240）的不需要的切换，并消除闪速存储器芯片中其他电路的过剩电流消耗和模式切换，CAM电路的输出被锁存。

公开(公告)号：US6134146A

公开(公告)日：2000-10-17

申请号：US166385

申请日：1998-10-05

申请人： Colin S. Bill ,  Jonathan S. Su ,  Takao Akaogi ,  Ravi P. Gutala

发明人： Colin S. Bill ,  Jonathan S. Su ,  Takao Akaogi ,  Ravi P. Gutala

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C8/08

摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power source for generating a low power supply voltage on the order of 3 V or less. A wordline driver includes a booster for boosting the supply voltage to produce a wordline read voltage which is higher than the supply voltage, and applying the wordline voltage to a wordline. An upper clamp limits a maximum value of the wordline voltage to prevent read disturb. The upper clamp can be configured to reduce an amount by which the maximum value varies with the supply voltage, or to limit the maximum value to substantially a predetermined value. A lower clamp limits the wordline voltage to a minimum value which is higher than the supply voltage and lower than the maximum value for a predetermined length of time at the beginning of the read operation to ensure that the cells have sufficient read current and to reduce the amount by which the minimum value varies with the supply voltage.

摘要翻译： 闪存电可擦除可编程只读存储器（EEPROM）包括多个浮栅晶体管存储单元，连接到单元的多个字线和用于产生大约3V或更小的低电源电压的电源 。 字线驱动器包括用于升高电源电压的升压器，以产生高于电源电压的字线读取电压，并将字线电压施加到字线。 上限钳位限制字线电压的最大值，以防止读取干扰。 上夹具可以被配置为减小最大值随着电源电压而变化的量，或者将最大值限制为基本上预定值。 在读取操作开始时，下限钳位将字线电压限制在比电源电压高并且低于预定时间长度的最小值的最小值，以确保单元具有足够的读取电流并且减少 最小值随着电源电压而变化的量。

公开(公告)号：US6125058A

公开(公告)日：2000-09-26

申请号：US421982

申请日：1999-10-19

申请人： Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akaogi ,  Johnny C. Chen

发明人： Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akaogi ,  Johnny C. Chen

IPC分类号： G11C7/06 ,  G11C7/20 ,  G11C16/28 ,  G11C16/32 ,  G11C29/02 ,  G11C29/50 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C29/026 ,  G11C16/28 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C7/062 ,  G11C7/20 ,  G11C16/04 ,  G11C2216/22

摘要： A system for optimizing the equalization pulse of a read sense amplifier is disclosed. A number of capacitor circuits are provided that can be coupled to a timing circuit in a variety of combinations. The different combinations of coupled and decoupled capacitor circuits result in different durational lengths of the equalization pulse. A testing sequence determines the optimal durational length of the equalization pulse by testing the different combinations of coupled capacitors. The optimal combination is then permanently stored in attribute cells for optimizing the equalization pulse in normal operation.

摘要翻译： 公开了一种用于优化读出放大器的均衡脉冲的系统。 提供了多个电容器电路，其可以以各种组合耦合到定时电路。 耦合和去耦合电容电路的不同组合导致均衡脉冲的不同持续时间长度。 测试序列通过测试耦合电容器的不同组合来确定均衡脉冲的最佳持续时间长度。 然后将最优组合永久存储在属性单元中，以在正常操作中优化均衡脉冲。

公开(公告)号：US6104667A

公开(公告)日：2000-08-15

申请号：US365075

申请日：1999-07-30

申请人： Takao Akaogi

发明人： Takao Akaogi

IPC分类号： G11C8/18 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

CPC分类号： G11C16/32 ,  G11C16/08 ,  G11C16/30 ,  G11C8/18

摘要： A clock control circuit receives an external clock signal and generates an internal clock signal. Through use of internal programming and an external trigger signal, the clock control circuit blocks out one or more of the clock cycles of the external clock signal to generate the internal clock signal. The clock control circuit can be used in any semiconductor device, and especially in synchronous flash memory devices with a burst operation. In the synchronous flash memory devices, one or more of the internal clock cycles are blocked out to account for increased delays during certain data sensing operations such as word line switching during data reading. In the synchronous flash memory devices, the sensed data is stored in input/output buffers and transferred out synchronously to the external clock signal.

摘要翻译： 时钟控制电路接收外部时钟信号并产生内部时钟信号。 通过使用内部编程和外部触发信号，时钟控制电路阻挡外部时钟信号的一个或多个时钟周期，以产生内部时钟信号。 时钟控制电路可用于任何半导体器件，特别是在具有突发操作的同步闪存器件中。 在同步闪速存储器件中，一个或多个内部时钟周期被阻止以考虑在某些数据检测操作期间增加的延迟，例如在数据读取期间的字线切换。 在同步闪速存储器件中，感测数据被存储在输入/输出缓冲器中并与外部时钟信号同步传送出去。

公开(公告)号：US5701274A

公开(公告)日：1997-12-23

申请号：US466665

申请日：1995-06-06

申请人： Takao Akaogi ,  Masanobu Yoshida

发明人： Takao Akaogi ,  Masanobu Yoshida

IPC分类号： G11C17/00 ,  G11C5/00 ,  G11C5/14 ,  G11C16/02 ,  G11C16/06 ,  G11C16/20 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  G11C8/00

CPC分类号： G11C5/145 ,  G11C16/20

摘要： A semiconductor device has a function of reading device information specific to the device as and when required. The semiconductor device has storage units for storing plural pieces of device information and a selector for selecting a predetermined one of the information pieces stored in the storage units when a device information read mode is set, so that the read information may match device data such as a manufacturer name and part name printed on the semiconductor device.

摘要翻译： 半导体器件具有在需要时读取器件特定信息的功能。 该半导体装置具有用于存储多条设备信息的存储单元和用于当设置设备信息读取模式时选择存储在存储单元中的预定的一个信息段的选择器，使得读取的信息可以匹配诸如 印刷在半导体器件上的制造商名称和部件名称。

公开(公告)号：US5402383A

公开(公告)日：1995-03-28

申请号：US078818

申请日：1993-06-21

申请人： Takao Akaogi

发明人： Takao Akaogi

IPC分类号： G06F12/00 ,  G11C16/02 ,  G11C16/12 ,  G11C16/16 ,  G11C17/00 ,  G11C13/00

CPC分类号： G11C16/16 ,  G11C16/12

摘要： An electrically erasable non-volatile semiconductor memory device has a memory cell array, a first erase unit, a second erase unit, and an operation mode establish unit. The erasing operation of the second erase unit is independently carried out of the erasing operation of the first erase unit. When a first operation mode is established by the operation mode establish unit, the second erase unit is inactivated, and the erasing operation of the memory cell array is only carried out by the first erase unit. On the other hand, when a second operation mode is established by the operation mode establish unit, the erasing operation of the first erase unit for a part of the memory cell array is disable, and the second erase unit is activated and the erasing operation for the part of the memory cell array is carried out by the second erase unit. Therefore, the change between a boot block type flash memory and normal type flash memory can be realized only by changing an establish value of the operation mode establish unit. Consequently, when developing both boot block type flash memory and normal type flash memory, these two types of flash memories can be obtained by using the same chip or by carrying out only minimum changes, so that the developing processes can be greatly decreased.

摘要翻译： 电可擦除非易失性半导体存储器件具有存储单元阵列，第一擦除单元，第二擦除单元和操作模式建立单元。 第二擦除单元的擦除操作独立地执行第一擦除单元的擦除操作。 当由操作模式建立单元建立第一操作模式时，第二擦除单元被禁用，并且存储单元阵列的擦除操作仅由第一擦除单元执行。 另一方面，当通过操作模式建立单元建立第二操作模式时，对于存储单元阵列的一部分的第一擦除单元的擦除操作被禁用，并且第二擦除单元被激活，并且擦除操作 存储单元阵列的一部分由第二擦除单元执行。 因此，仅通过改变操作模式建立单元的建立值才能实现引导块型闪速存储器与正常型闪速存储器之间的变化。 因此，当开发引导块型闪速存储器和普通型闪速存储器时，可以通过使用相同的芯片或仅通过执行最小变化来获得这两种类型的闪存，从而可以大大降低显影过程。

公开(公告)号：US5280451A

公开(公告)日：1994-01-18

申请号：US656501

申请日：1991-02-19

申请人： Takao Akaogi

发明人： Takao Akaogi

IPC分类号： G11C17/00 ,  G11C5/00 ,  G11C16/20 ,  G11C29/00

CPC分类号： G11C16/20 ,  G11C5/00

摘要： A signature circuit stores signature information indicative of one of a plurality of device functions of a non-volatile memory device which includes first memory cells which are respectively coupled to one of a plurality of word lines and to one of a plurality of bit lines. The signature circuit includes second memory cells which are respectively connected to the bit lines which are grouped into a plurality of blocks, at least one predetermined word line which is provided exclusively for the second memory cells and is connected to each of the memory cells, and a selecting circuit coupled to the bit lines for selecting one of the blocks. The second memory cells in each of the blocks store one kind of signature information, so that a number of blocks is equal to a number of kinds of signature information that can be stored in the signature circuit.

摘要翻译： 签名电路存储指示非易失性存储器件的多个器件功能之一的签名信息，该非易失性存储器件包括分别耦合到多条字线之一和多条位线之一的第一存储器单元。 签名电路包括分别连接到分组为多个块的位线的第二存储器单元，专门为第二存储单元提供并连接到每个存储器单元的至少一个预定字线，以及 耦合到所述位线的选择电路，用于选择所述块中的一个。 每个块中的第二存储单元存储一种签名信息，使得多个块等于可以存储在签名电路中的签名信息的种类数量。