公开(公告)号：US06525400B2

公开(公告)日：2003-02-25

申请号：US10078506

申请日：2002-02-21

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L2900

CPC分类号： H01L29/7883 ,  H01L21/28273

摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

公开(公告)号：US06365458B1

公开(公告)日：2002-04-02

申请号：US09661572

申请日：2000-09-14

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

摘要翻译： 在半导体衬底的表面上形成栅极氧化膜。 在对应于隧道区域的部分中形成厚度小于栅极绝缘膜厚度的隧道绝缘膜。 在栅极绝缘膜上形成杂质浓度低的第一硅膜。 在第一硅膜上形成杂质浓度高于第一硅膜的第二硅膜，以便与第一硅膜连接。 通过绝缘膜在第二硅膜上形成第三硅膜。 第二和第三硅膜分别形成浮动和控制栅极，从而形成半导体存储器件。

公开(公告)号：US06244112B1

公开(公告)日：2001-06-12

申请号：US09457350

申请日：1999-12-09

申请人： Tetsuo Fujii

发明人： Tetsuo Fujii

IPC分类号： G01P15125

CPC分类号： G01P15/125 ,  G01P15/0802 ,  G01P2015/0817

摘要： A single crystal silicon substrate (1) is bonded through an SiO2 film (9) to a single crystal silicon substrate (8), and the single crystal silicon substrate (1) is made into a thin film. A cantilever (13) is formed on the single crystal silicon substrate (1), and the thickness of the cantilever (13) in a direction parallel to the surface of the single crystal silicon substrate (1) is made smaller than the thickness of the cantilever in the direction of the depth of the single crystal silicon substrate (1), and movable in a direction parallel to the substrate surface. In addition, the surface of the cantilever (13) and the part of the single crystal silicon substrate (1), opposing the cantilever (13), are, respectively, coated with an SiO2 film (5), so that an electrode short circuit is prevented in a capacity-type sensor. In addition, a signal-processing circuit (10) is formed on the single crystal silicon substrate (1), so that signal processing is performed as the cantilever (13) moves.

摘要翻译： 单晶硅基板（1）通过SiO 2膜（9）与单晶硅基板（8）接合，将单晶硅基板（1）制成薄膜。 在单晶硅衬底（1）上形成悬臂（13），并且使悬臂（13）的平行于单晶硅衬底（1）的表面的方向的厚度小于单晶硅衬底 在单晶硅衬底（1）的深度方向上的悬臂，并且可以在平行于衬底表面的方向上移动。 此外，悬臂（13）的表面和单晶硅衬底（1）的与悬臂（13）相对的部分分别涂覆有SiO 2膜（5），使得电极短路 在容量型传感器中被阻止。 此外，在单晶硅衬底（1）上形成信号处理电路（10），从而当悬臂（13）移动时进行信号处理。

公开(公告)号：US06227049B1

公开(公告)日：2001-05-08

申请号：US08566600

申请日：1995-12-04

申请人： Tetsuo Fujii

发明人： Tetsuo Fujii

IPC分类号： G01P15125

CPC分类号： G01P15/125 ,  G01P15/0802 ,  G01P2015/0817

摘要： A single crystal silicon substrate (1) is bonded through an SiO2 film (9) to a single crystal silicon substrate (8), and the single crystal silicon substrate (1) is made into a thin film. A cantilever (13) is formed on the single crystal silicon substrate (1), and the thickness of the cantilever (13) in a direction parallel to the surface of the single crystal silicon substrate (1) is made smaller than the thickness of the cantilever in the direction of the depth of the single crystal silicon substrate (1), and movable in a direction parallel to the substrate surface. In addition, the surface of the cantilever (13) and the part of the single crystal silicon substrate (1), opposing the cantilever (13), are, respectively, coated with an SiO2 film (5), so that an electrode short circuit is prevented in a capacity-type sensor. In addition, a signal-processing circuit (10) is formed on the single crystal silicon substrate (1), so that signal processing is performed as the cantilever (13) moves.

公开(公告)号：US5872024A

公开(公告)日：1999-02-16

申请号：US834129

申请日：1997-04-14

申请人： Tetsuo Fujii ,  Masahito Imai

发明人： Tetsuo Fujii ,  Masahito Imai

IPC分类号： B81B7/00 ,  C07C303/32 ,  C07C303/44 ,  C07C309/17 ,  G01C19/56 ,  G01C19/5656 ,  G01C19/5719 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46

CPC分类号： B81B7/0006 ,  C07C303/32 ,  C07C303/44 ,  G01C19/56 ,  G01C19/5656 ,  G01C19/5719 ,  G01P15/0802 ,  G01P15/125 ,  B81B2201/0235 ,  G01P2015/0817 ,  G01P2015/0828 ,  Y10T29/49002 ,  Y10T29/49004

摘要： A semiconductor mechanical sensor having a new structure in which a S/N ratio is improved. In the central portion of a silicon substrate 1, a recess portion 2 is formed which includes a beam structure. A weight is formed at the tip of the beam, and in the bottom surface of the weight in the bottom surface of the recess portion 2 facing the same, an electrode 5 is formed. An alternating current electric power is applied between the weight portion 4 and the electrode 5 so that static electricity is created and the weight is excited by the static electricity. In an axial direction which is perpendicular to the direction of the excitation of the weight, an electrode 6 is disposed to face one surface of the weight and a wall surface of the substrate which faces the same. A charge in a capacitance between the facing electrodes is electrically detected, and therefore, a change in a physical force acting in the same direction is detected.

摘要翻译： 具有S / N比提高的新结构的半导体机械传感器。 在硅衬底1的中心部分，形成包括梁结构的凹部2。 在梁的尖端处形成重物，并且在凹部2的底面中的重物的底面中，重物形成为电极5。 在重量部分4和电极5之间施加交流电力，从而产生静电，并且重量被静电激励。 在与重量的激励方向垂直的轴向方向上，电极6设置为面对重物的一个表面和面向其的基板的壁表面。 对面对电极之间电容的电荷被电检测，因此检测到以相同方向作用的物理力的变化。

公开(公告)号：US5320705A

公开(公告)日：1994-06-14

申请号：US108498

申请日：1993-08-18

申请人： Tetsuo Fujii ,  Yoshitaka Gotoh ,  Susumu Kuroyanagi ,  Osamu Ina

发明人： Tetsuo Fujii ,  Yoshitaka Gotoh ,  Susumu Kuroyanagi ,  Osamu Ina

IPC分类号： G01L9/00 ,  H01L27/20 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： G01L9/0042 ,  G01L19/147 ,  G01L9/0054 ,  H01L27/20 ,  Y10T29/42 ,  Y10T29/49103

摘要： A semiconductor pressure sensor of this invention is intended to provide a semiconductor pressure sensor having an excellent electrical isolation between the supporting means of the semiconductor pressure sensor and the semiconductor substrate, the semiconductor pressure sensor basically comprising a semiconductor substrate having a first semiconductor region in which; at least a semiconductor device is formed, a second semiconductor region and an isolated layer buried between the first and second semiconductor regions, a cavity provided in the second semiconductor region, the opening thereof existing on the mail surface of the second semiconductor region and a strain detecting portion consisting of the semiconductor device and provided in the first semiconductor region opposite to the cavity. The semiconductor pressure sensor is featured in that at least one of the outer peripheral side surfaces of the first and the second semiconductor regions is formed inside of the outermost peripheral side surface of the isolation layer.

摘要翻译： 本发明的半导体压力传感器旨在提供一种半导体压力传感器，其具有在半导体压力传感器的支撑装置和半导体衬底之间具有优异的电绝缘性，半导体压力传感器基本上包括具有第一半导体区域的半导体衬底， ; 形成至少一个半导体器件，第二半导体区域和埋在第一和第二半导体区域之间的隔离层，设置在第二半导体区域中的空腔，存在于第二半导体区域的邮件表面上的开口和应变 检测部分由半导体器件组成并设置在与空腔相对的第一半导体区域中。 半导体压力传感器的特征在于，第一半导体区域和第二半导体区域的至少一个外周侧表面形成在隔离层的最外周侧表面的内部。

公开(公告)号：US5313836A

公开(公告)日：1994-05-24

申请号：US996474

申请日：1992-12-23

申请人： Tetsuo Fujii ,  Susumu Kuroyanagi ,  Yoshitaka Gotoh

发明人： Tetsuo Fujii ,  Susumu Kuroyanagi ,  Yoshitaka Gotoh

IPC分类号： G01P15/12 ,  G01P15/02 ,  G01P15/08 ,  H01L29/84

CPC分类号： G01P15/02 ,  G01P15/0802 ,  G01P15/123 ,  G01P2015/0828

摘要： A semiconductor sensor for an accelerometer including a beam portion, consisting of a thin beam portion and a thick beam portion and supported by a solid member through the end of the thin beam portion, and a stopper portion provided at a position on an imaginary line along which a center of gravity of the thick beam portion moves. These components are integrally formed in a silicon substrate. Excessive displacement of the beam portion when excessive acceleration is applied is effectively suppressed by the stopper portion, and breakage of the thin beam portion due to excessive acceleration can be avoided.

摘要翻译： 一种用于加速度计的半导体传感器，其包括梁部分，该梁部分由薄梁部分和厚梁部分组成，并且通过薄梁部分的端部由实心部件支撑，以及设置在假想线上的位置处的止动部分 其中厚梁部分的重心移动。 这些部件一体地形成在硅衬底中。 当施加过大的加速度时，梁部分的过大位移被止动部分有效地抑制，并且可以避免由于过度的加速度引起的薄梁部分的断裂。

公开(公告)号：US5017505A

公开(公告)日：1991-05-21

申请号：US313898

申请日：1989-02-23

申请人： Tetsuo Fujii ,  Toshio Sakakibara ,  Nobuyoshi Sakakibara

发明人： Tetsuo Fujii ,  Toshio Sakakibara ,  Nobuyoshi Sakakibara

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  Y10S438/964

摘要： A first polysilicon film serving as an erase gate is deposited on the major surface of a semiconductor substrate on which a field oxide film is formed, so that the surface of the first polysilicon film is roughened. The surface of the first polysilicon film is thermally oxidized to form a first thermal oxide film thereon. During the oxidation, the roughened surface of the first polysilicon film is flattened, and is duplicated by the surface of the first thermal oxide film. A second polysilicon film is deposited on the roughened surface of the first thermal oxide film. The back surface of the second polysilicon film is roughened by the roughened surface of the first thermal oxide film. In this case, the surface of the second polysilicon film is also roughened. The roughened surface of the second polysilicon film is thermally oxidized in the same manner as described above to flatten its surface and to form a second thermal oxide film, the surface of which is roughened. A third polysilicon film serving as a write gate is formed on the second thermal oxide film.

摘要翻译： 用作擦除栅极的第一多晶硅膜沉积在其上形成有场氧化膜的半导体衬底的主表面上，使得第一多晶硅膜的表面被粗糙化。 第一多晶硅膜的表面被热氧化以在其上形成第一热氧化膜。 在氧化期间，第一多晶硅膜的粗糙化表面变平，并被第一热氧化膜的表面复制。 在第一热氧化膜的粗糙化表面上沉积第二多晶硅膜。 第二多晶硅膜的背面被第一热氧化膜的粗糙化表面粗糙化。 在这种情况下，第二多晶硅膜的表面也被粗糙化。 第二多晶硅膜的粗糙化表面以与上述相同的方式被热氧化以使其表面变平，并形成第二热氧化膜，其表面被粗糙化。 在第二热氧化膜上形成用作写入栅极的第三多晶硅膜。

公开(公告)号：US4774556A

公开(公告)日：1988-09-27

申请号：US887625

申请日：1986-07-21

申请人： Tetsuo Fujii ,  Nobuyoshi Sakakibara ,  Toshio Sakakibara ,  Hiroshi Iwasaki

发明人： Tetsuo Fujii ,  Nobuyoshi Sakakibara ,  Toshio Sakakibara ,  Hiroshi Iwasaki

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78 ,  H01L29/86

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L27/115 ,  H01L29/4236

摘要： A non-volatile semiconductor memory device comprises a semiconductor substrate of a first conduction type, an impurity buried layer of a second conduction type formed at the surface of the semiconductor substrate for constituting either one of a drain region or a source region, an epitaxial layer of a second conduction type formed at the surface of said impurity buried layer, an insulatiang partition wall extended vertically from the surface of the epitaxial layer surrounding operation regions in the impurity buried layer for defining the operation regions therein, at least one electron holding portion extended vertically with a predetermined distance from the operation regions and disposed within the insulating partition wall apart from the operation region, the impurity buried layer or the drain region by an insulation film of such a thickness as causing a tunnel effect, control gates disposed within the insulation partition wall disposed on every electron holding portions on the side opposite to the operation regions and extended vertically with a certain gap from the electron maintaining portions, and a control gate disposed within the insulating partition wall on every electron holding portions on the opposite side to the operation region extended vertically and with a certain gap to the electron holding portions, and an impurity region of a second conduction type formed at the surface of the operation region for constituting the other of the drain region or the source region.

摘要翻译： 非易失性半导体存储器件包括：第一导电类型的半导体衬底，形成在半导体衬底的表面的第二导电类型的杂质掩埋层，用于构成漏极区域或源极区域中的任一个，外延层 形成在所述杂质掩埋层的表面上的第二导电类型的绝缘分隔壁，包围在所述杂质掩埋层中的围绕所述杂质掩埋层的操作区域的外延层的表面垂直延伸的绝缘隔壁，用于限定其中的操作区域，至少一个电子保持部分延伸 垂直于操作区域预定的距离并且设置在与操作区域隔离的绝缘分隔壁内，通过具有隧道效应的厚度的绝缘膜的杂质掩埋层或漏极区域，设置在绝缘体内的控制栅极 分隔壁设置在侧面上的每个电子保持部分上 e与操作区域相对并且与电子维持部分具有一定间隙垂直延伸;以及控制栅极，设置在绝缘分隔壁内的每个电子保持部分上，与操作区域相对的一侧垂直延伸并且具有一定间隙 电子保持部分和形成在用于构成漏极区域或源极区域中的另一个的操作区域的表面处的第二导电类型的杂质区域。

公开(公告)号：US08890252B2

公开(公告)日：2014-11-18

申请号：US13190798

申请日：2011-07-26

申请人： Hirotaka Saikaku ,  Tsuyoshi Yamamoto ,  Shoji Mizuno ,  Masakiyo Sumitomo ,  Tetsuo Fujii ,  Jun Sakakibara ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Rie Taguchi ,  Makoto Kuwahara

发明人： Hirotaka Saikaku ,  Tsuyoshi Yamamoto ,  Shoji Mizuno ,  Masakiyo Sumitomo ,  Tetsuo Fujii ,  Jun Sakakibara ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Rie Taguchi ,  Makoto Kuwahara

IPC分类号： H01L21/70 ,  H01L21/78 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/861 ,  H02M7/00

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7391 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7805 ,  H01L29/7819 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/861 ,  H01L2924/0002 ,  H02M7/003 ,  H01L2924/00

摘要： A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

摘要翻译： 一种半导体器件包括：具有漂移层的开关元件; 基地区 在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。