公开(公告)号：US07192792B2

公开(公告)日：2007-03-20

申请号：US11066592

申请日：2005-02-24

申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L21/66 ,  H01L31/111

CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use, including a method of changing an electrically programmable resistance cross point memory bit. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

摘要翻译： 提供了电阻式交叉点存储器件以及制造和使用方法，包括改变电可编程电阻交叉点存储器位的方法。 存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。 位于上电极和下电极的交叉点处的有源层内的位区域具有响应于一个或多个电压脉冲的施加而可以在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 提供存储器电路以帮助编程和读出位区域。

公开(公告)号：US06972211B2

公开(公告)日：2005-12-06

申请号：US10971263

申请日：2004-10-21

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  H10L21/00 ,  H10L21/20 ,  H10L21/3205 ,  H10L21/8222

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

摘要翻译： 提供了电阻式交叉点存储器件，以及制造和使用方法。 存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。 在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 在电阻性存储器材料和下部电极之间的界面处形成二极管，其可以形成为通过浅沟槽隔离彼此隔离的掺杂区域。 电阻交叉点存储器件通过在衬底内通过浅沟槽隔离彼此分离的线路形成一个极性，然后将相反极性的线的掺杂区域形成二极管来形成。 然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。 然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

公开(公告)号：US06940113B2

公开(公告)日：2005-09-06

申请号：US10971203

申请日：2004-10-21

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

摘要翻译： 提供了电阻式交叉点存储器件，以及制造和使用方法。 存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。 在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 在电阻性存储器材料和下部电极之间的界面处形成二极管，其可以形成为通过浅沟槽隔离彼此隔离的掺杂区域。 电阻交叉点存储器件通过在衬底内通过浅沟槽隔离彼此分离的线路形成一个极性，然后将相反极性的线的掺杂区域形成二极管来形成。 然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。 然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

公开(公告)号：US06876521B2

公开(公告)日：2005-04-05

申请号：US10705066

申请日：2003-11-10

申请人： Wei Pan ,  Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Wei Pan ,  Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01F10/193 ,  H01F21/00 ,  H01F41/24 ,  H01L21/02 ,  H01L27/08 ,  H01F5/00 ,  G11B5/127

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01F10/193 ,  H01F21/00 ,  H01F41/24 ,  H01L27/08 ,  H01L28/10 ,  Y10T29/4902

摘要： A solid-state inductor and a method for forming a solid-state inductor are provided. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) thin film overlying the bottom electrode; forming a top electrode overlying the CMR thin film; applying an electrical field treatment to the CMR thin film in the range of 0.4 to 1 megavolts per centimeter (MV/cm) with a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms); in response to the electrical field treatment, converting the CMR thin film into a CMR thin film inductor; applying a bias voltage between the top and bottom electrodes; and, in response to the applied bias voltage, creating an inductance between the top and bottom electrodes. When the applied bias voltage is varied, the inductance varies in response.

摘要翻译： 提供固态电感器和形成固态电感器的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）薄膜; 形成覆盖CMR薄膜的顶部电极; 以0.1纳秒（ns）至1毫秒（ms）的脉冲宽度在0.4至1兆伏特/厘米（MV / cm）范围内对CMR薄膜进行电场处理; 响应于电场处理，将CMR薄膜转换成CMR薄膜电感器; 在顶部和底部电极之间施加偏置电压; 并且响应于施加的偏置电压，在顶部和底部电极之间产生电感。 当施加的偏置电压变化时，电感响应变化。

公开(公告)号：US06673691B2

公开(公告)日：2004-01-06

申请号：US10256358

申请日：2002-09-26

申请人： Wei-Wei Zhuang ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC分类号： G11C1100

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  Y10S502/525

摘要： A method of changing the resistance of a perovskite metal oxide thin film device with a resistance-change-producing pulse includes changing the resistance of the device by varying the duration of a resistance-change-producing pulse.

摘要翻译： 通过电阻变化产生脉冲改变钙钛矿金属氧化物薄膜器件的电阻的方法包括通过改变电阻变化产生脉冲的持续时间来改变器件的电阻。

公开(公告)号：US06531371B2

公开(公告)日：2003-03-11

申请号：US09894922

申请日：2001-06-28

申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L2120

CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

摘要翻译： 提供了电阻式交叉点存储器件以及制造和使用方法。 存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。 在上电极和下电极的交叉点处位于有源层内的位区域具有响应于施加一个或更多个电压脉冲而可以在值范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 提供存储器电路以帮助编程和读出位区域。

公开(公告)号：US06441417B1

公开(公告)日：2002-08-27

申请号：US09820022

申请日：2001-03-28

申请人： Fengyan Zhang ,  Yanjun Ma ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Yanjun Ma ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC分类号： H01L2972

CPC分类号： H01L21/28291 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/516

摘要： A thin film structure includes a substantially single-phase, c-axis PGO film on an insulator for use in metal ferroelectric insulator semiconductor single transistor non-volatile memory applications. The PGO on insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. In a preferred embodiment, the PGO film is deposited on a Zirconium Oxide insulator layer.

摘要翻译： 薄膜结构包括用于金属铁电绝缘体半导体单晶体管非易失性存储器应用的绝缘体上的基本单相c轴PGO膜。 PGO绝缘体结构也可用于电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件中。 在优选实施例中，PGO膜沉积在氧化锆绝缘体层上。

公开(公告)号：US07723729B2

公开(公告)日：2010-05-25

申请号：US12036396

申请日：2008-02-25

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L31/0312 ,  H01L29/20 ,  H01L29/06

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/045 ,  H01L29/0673

摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where x≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.

摘要翻译： 提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。 该方法形成Si衬底。 在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。 化合物半导体选择性沉积在Si纳米线尖端上。 横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。 通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或SiXNY，其中x和nlE; 3和Y和nlE; 4。 化合物半导体可以是GaN，GaAs，GaAlN或SiC。 在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。

公开(公告)号：US20080164569A1

公开(公告)日：2008-07-10

申请号：US11582275

申请日：2006-10-16

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L29/00

CPC分类号： H01L27/15 ,  H01L33/0004 ,  H01L33/343

摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.

摘要翻译： 一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。 根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。

公开(公告)号：US07358160B2

公开(公告)日：2008-04-15

申请号：US11481437

申请日：2006-07-06

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L21/36

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02538 ,  H01L21/7624

摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where X≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.

摘要翻译： 提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。 该方法形成Si衬底。 在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。 化合物半导体选择性沉积在Si纳米线尖端上。 横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。 通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或Si X N Y ，其中 X <= 3 AND Y <= 4。 化合物半导体可以是GaN，GaAs，GaAlN或SiC。 在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。