公开(公告)号：US20050207710A1

公开(公告)日：2005-09-22

申请号：US11046551

申请日：2005-01-28

申请人： Tsuyoshi Tanaka ,  Tomoyuki Hirose ,  Kaichiro Nakashima ,  Michifumi Shoda

发明人： Tsuyoshi Tanaka ,  Tomoyuki Hirose ,  Kaichiro Nakashima ,  Michifumi Shoda

IPC分类号： G02B6/36 ,  G02B6/42

CPC分类号： G02B6/421 ,  G02B6/4209 ,  G02B6/4292

摘要： In a semiconductor laser module with an optical isolator where the form of a metal holder for holding a fiber stub varies, optical-isolator parts are miniaturized and unified, simplifying product management, reducing delivery time and cost. A fiber stub with an optical isolator is provided in such a manner that a stepped surface is formed on an end surface of a ferrule, where an optical fiber has been inserted and secured to a through hole formed at the center of the ferrule. The fiber stub is formed by attaching an optical isolator element composed of a polarizer and a Faraday rotator to the stepped surface.

摘要翻译： 在具有用于保持光纤短截线的金属保持器的形式的光隔离器的半导体激光器模块中，光隔离器部件被小型化和统一化，简化了产品管理，减少了交付时间和成本。 提供了具有光隔离器的光纤短截线，使得在套圈的端面上形成台阶表面，其中光纤被插入并固定到形成在套圈中心的通孔。 通过将由偏振器和法拉第旋转器组成的光隔离器元件附接到台阶表面来形成光纤短截线。

公开(公告)号：US20050201129A1

公开(公告)日：2005-09-15

申请号：US11057615

申请日：2005-02-15

申请人： Junnosuke Nakatsugawa ,  Tsuyoshi Tanaka ,  Kenji Sakurai ,  Tunehiro Endo

发明人： Junnosuke Nakatsugawa ,  Tsuyoshi Tanaka ,  Kenji Sakurai ,  Tunehiro Endo

IPC分类号： H02M1/12 ,  H02M7/48 ,  H02P6/06 ,  H02P6/08

CPC分类号： H02P6/10 ,  H02P6/182 ,  H02P27/08

摘要： A control apparatus and a semiconductor apparatus of AC motors capable of reducing torque ripple with a comparatively simple circuit corresponding to a high withstand voltage and capable of driving a motor at high efficiency even when the rotational speed or load has changed. The control apparatus detects first phase signals fixed in relative phase to induced voltages of the motor and current polarity signals, recognizes phase differences between them, generates second phase signals so as to make the phase differences approach zero to drive the motor at high efficiency, generates modulation wave signals having quasi-sinusoidal waveforms or trapezoidal waveforms on the basis of the second phase signals, compares the modulation wave signals with a carrier wave signal, and conducts PWM control on an inverter.

摘要翻译： 一种AC电动机的控制装置和半导体装置，其能够以对应于高耐受电压的比较简单的电路来减小转矩脉动，并且即使当转速或负载已经改变时也能够以高效率驱动电动机。 控制装置检测相对于电动机的感应电压和电流极性信号相对固定的第一相位信号，识别它们之间的相位差，产生第二相位信号，以使相位接近零，以高效率驱动电动机，产生 基于第二相位信号具有准正弦波形或梯形波形的调制波信号将调制波信号与载波信号进行比较，并对逆变器进行PWM控制。

公开(公告)号：US06933542B2

公开(公告)日：2005-08-23

申请号：US10768040

申请日：2004-02-02

申请人： Hidetoshi Ishida ,  Tsuyoshi Tanaka

发明人： Hidetoshi Ishida ,  Tsuyoshi Tanaka

IPC分类号： H01L21/335 ,  H01L27/06 ,  H01L29/778 ,  H01L31/109 ,  H01L29/739

CPC分类号： H01L29/66462 ,  H01L27/0605 ,  H01L29/7783

摘要： A channel layer made of undoped InGaAs, a carrier supply layer made of n-type AlGaAs, a Schottky layer made of disordered InGaP without a natural superlattice structure, and a cap layer made of GaAs are successively stacked on a compound semiconductor substrate. A gate electrode is formed on a part of the Schottky layer exposed at the opening of the cap layer. Source and dram electrodes are formed on the cap layer. The thickness of the Schottky layer is set at about 8 nm or less. As a result, the reverse breakdown voltage of the gate electrode becomes larger than that in the case of a Schottky layer made of AlGaAs.

摘要翻译： 由n型AlGaAs构成的载流子供给层，由天然超晶格结构的无序InGaP构成的肖特基以及由GaAs构成的盖层构成的沟道层依次层叠在化合物半导体基板上。 栅极电极形成在暴露在盖层开口处的肖特基层的一部分上。 源极和引脚电极形成在盖层上。 肖特基层的厚度设定为约8nm以下。 结果，栅电极的反向击穿电压变得大于由AlGaAs制成的肖特基层的情况。

公开(公告)号：US20050082568A1

公开(公告)日：2005-04-21

申请号：US10862452

申请日：2004-06-08

申请人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

发明人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

IPC分类号： H01L21/28 ,  H01L21/338 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

摘要翻译： 半导体器件具有蓝宝石衬底，设置在蓝宝石衬底上的由GaN制成的半导体层，设置在半导体层上的多层膜和与该多层膜欧姆接触的电极。 已经通过交替地堆叠具有不同量的极化或不同量的自发极化的两种类型的半导体层，并且每个含有n型杂质，以便在两种类型的半导体层之间的界面处诱导电子而形成多层膜。 这允许电极和多层膜之间的接触电阻和电流传输路径中的寄生电阻降低到比常规半导体器件中的值更低的值。

公开(公告)号：US06864708B2

公开(公告)日：2005-03-08

申请号：US10200719

申请日：2002-07-22

申请人： Hiroshi Takahashi ,  Akihiro Takegama ,  Yutaka Toyonoh ,  Kaoru Awaka ,  Tsuyoshi Tanaka ,  Rimon Ikeno

发明人： Hiroshi Takahashi ,  Akihiro Takegama ,  Yutaka Toyonoh ,  Kaoru Awaka ,  Tsuyoshi Tanaka ,  Rimon Ikeno

IPC分类号： H01L21/822 ,  G11C5/14 ,  H01L27/04 ,  H01L31/0336 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0948

CPC分类号： H03K19/00315 ,  G11C5/14 ,  H03K19/0016

摘要： A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability. While in a standby status, a voltage equal to source voltage Vdd is applied to the gate of transistor MP0, a voltage lower than the source voltage is applied to the source, and bulk bias voltage VB equal to or higher than source voltage Vdd is applied to the channel region in order to minimize the drain current of transistor MP0, so that current path of logic circuit 10 is cut off, and the occurrence of leakage current is suppressed.

公开(公告)号：US20050001235A1

公开(公告)日：2005-01-06

申请号：US10834362

申请日：2004-04-29

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/338 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328 ,  H01S5/30

CPC分类号： H01L29/7787 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766

摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1-yN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

摘要翻译： 半导体器件具有：形成在导电基板上并由高电阻的Al x Ga 1-x N构成的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N制成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。 源电极被填充在设置在缓冲层和元件形成层中的通孔中，因此电连接到导电基板。

公开(公告)号：US06789173B1

公开(公告)日：2004-09-07

申请号：US09585390

申请日：2000-06-02

申请人： Tsuyoshi Tanaka ,  Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai

发明人： Tsuyoshi Tanaka ,  Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai

IPC分类号： G06F1200

CPC分类号： G06F12/0813

摘要： In a multiprocessor system of a main memory shared type having a plurality of nodes connected each other through signal lines; each of the plurality of nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones of the nodes other than its own node. The node controller has a communication controller for controlling communication interface between the plurality of nodes, a crossbar for determining a processing sequence of memory access issued from at least one of the plurality of nodes to be directed to the main memories of the plurality of nodes, and crossbar controller for making valid or invalid the crossbar.

摘要翻译： 在具有通过信号线彼此连接的多个节点的主存储器共享类型的多处理器系统中; 所述多个节点中的每一个包括其中具有高速缓存的CPU，主存储器和节点控制器，用于执行CPU，主存储器以及除了其自身节点之外的节点之间的通信控制。 节点控制器具有用于控制多个节点之间的通信接口的通信控制器，用于确定从多个节点中的至少一个节点发出的指向多个节点的主存储器的存储器访问的处理顺序的交叉开关， 和横杆控制器使横梁有效或无效。

公开(公告)号：US06769819B2

公开(公告)日：2004-08-03

申请号：US09821539

申请日：2001-03-28

申请人： Tsuyoshi Tanaka ,  Daisuke Komada ,  Shiro Yonekura

发明人： Tsuyoshi Tanaka ,  Daisuke Komada ,  Shiro Yonekura

IPC分类号： G02B642

CPC分类号： G02B6/4226 ,  G02B6/4237 ,  G02B6/424 ,  G02B6/4248 ,  G02B6/4251 ,  G02B6/4271

摘要： An optical device module is provided which includes an optical device, an optical fiber an end of which is optically coupled to the optical device, a package containing the optical device and the optical fiber, and an insertion tube fixed air-tightly through the wall of the package, the optical fiber extending through the insertion tube out of the package, wherein the end portion of the optical fiber is offset with respect to the fixed portion, by the insertion tube, of the optical fiber to bend the optical fiber between the end portion and the fixed portion of the optical fiber, then avoiding the displacement of the end of the fiber to be coupled to the optical device due to a change in environment temperatures of the module, and minimize the temperature dependence of device performance. Further, the optical device module may be fabricated such that the end portion of the optical fiber is fixed to a ferrule which is fixed to a ferrule holder which is capable to be deformed plastically, whereby the optical axes of the optical device and the end of the optical fiber can readily be adjusted accurately after assembly.

摘要翻译： 提供了一种光学器件模块，其包括光学器件，光纤，其光端与光学器件光耦合，包含光学器件和光纤的封装以及气密地穿过 所述光纤通过所述插入管从所述封装中延伸，其中所述光纤的端部通过所述光纤的所述插入管相对于所述固定部分偏移以将所述光纤弯曲在所述端部之间 部分和光纤的固定部分，然后避免由于模块的环境温度的变化而耦合到光学装置的光纤的端部的位移，并且最小化器件性能的温度依赖性。 此外，光学器件模块可以被制造成使得光纤的端部固定到固定到能够塑性变形的套圈保持器的套圈，由此光学器件的光轴和端部 组装后光纤可以很容易地精确调整。

公开(公告)号：US06376898B1

公开(公告)日：2002-04-23

申请号：US09631104

申请日：2000-08-01

申请人： Tomoya Uda ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara

发明人： Tomoya Uda ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara

IPC分类号： H01L2973

CPC分类号： H01L29/0692 ,  H01L27/0207 ,  H01L27/082 ,  H01L29/737

摘要： An inventive semiconductor integrated circuit device includes multiple transistor banks over a substrate. The banks are arranged to be substantially parallel to each other in a planar layout of the device. Each said bank includes a plurality of unit transistors, each including a base, an emitter and a collector. In the planar layout of the device, a position of a first one of the transistors is shifted from a position of a second one of the transistors in a direction in which the banks extend. The first and second transistors belong to first and second ones of the banks, respectively, which are adjacent to each other. The second transistor is closer to the first transistor than any other transistor in the second bank.

摘要翻译： 本发明的半导体集成电路器件包括在衬底上的多个晶体管组。 这些堤被布置成在设备的平面布局中彼此基本平行。 每个所述存储体包括多个单元晶体管，每个单元晶体管包括基极，发射极和集电极。 在器件的平面布局中，晶体管中的第一个晶体管的位置沿着两个晶体管延伸的方向从第二晶体管的位置移位。 第一和第二晶体管分别属于彼此相邻的第一和第二晶体管。 第二晶体管比第二组中的任何其它晶体管更靠近第一晶体管。

公开(公告)号：US06365513B1

公开(公告)日：2002-04-02

申请号：US09162232

申请日：1998-09-29

申请人： Hidetoshi Furukawa ,  Atsushi Noma ,  Tsuyoshi Tanaka ,  Hidetoshi Ishida ,  Daisuke Ueda

发明人： Hidetoshi Furukawa ,  Atsushi Noma ,  Tsuyoshi Tanaka ,  Hidetoshi Ishida ,  Daisuke Ueda

IPC分类号： H01L2166

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

摘要翻译： 在衬底中形成具有底部的通孔，然后在通孔的至少一个侧壁上形成导体层。 此后，通过去除衬底的与形成通孔的衬底的另一部分相对的部分使得导体层暴露而使衬底变薄。