公开(公告)号：US5780358A

公开(公告)日：1998-07-14

申请号：US630112

申请日：1996-04-08

申请人： Mei Sheng Zhou ,  Chu Ron-Fu

发明人： Mei Sheng Zhou ,  Chu Ron-Fu

IPC分类号： C09K3/14 ,  H01L21/321 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/7684 ,  C09K3/1472 ,  H01L21/3212

摘要： A Chemical-Mechanical Polish (CMP) planarizing method and a Chemical-Mechanical Polish (CMP) slurry composition for Chemical-Mechanical Polish (CMP) planarizing of copper metal and copper metal alloy layers within integrated circuits. There is first provided a semiconductor substrate having formed upon its surface a patterned substrate layer. Formed within and upon the patterned substrate layer is a blanket copper metal layer or a blanket copper metal alloy layer. The blanket copper metal layer or blanket copper metal alloy layer is then planarized through a Chemical-Mechanical Polish (CMP) planarizing method employing a Chemical-Mechanical Polish (CMP) slurry composition. The Chemical-Mechanical Polish (CMP) slurry composition comprises a non-aqueous coordinating solvent and a halogen radical producing specie.

摘要翻译： 化学机械抛光（CMP）平面化方法和化学机械抛光（CMP）浆料组合物用于集成电路中铜金属和铜金属合金层的化学机械抛光（CMP）平面化。 首先提供了在其表面上形成图案化衬底层的半导体衬底。 形成在图案化衬底层的内部和之上的是铜层金属层或覆盖铜金属合金层。 然后通过使用化学机械抛光（CMP）浆料组合物的化学机械抛光（CMP）平面化方法将橡皮布铜金属层或橡皮布铜金属合金层平坦化。 化学机械抛光（CMP）浆料组合物包含非水配位溶剂和卤素原子产生物。

公开(公告)号：US20090156010A1

公开(公告)日：2009-06-18

申请号：US11959034

申请日：2007-12-18

申请人： Xiang Hu ,  Hai Cong ,  Pradeep Yelehanka ,  Mei Sheng Zhou

发明人： Xiang Hu ,  Hai Cong ,  Pradeep Yelehanka ,  Mei Sheng Zhou

IPC分类号： H01L21/302

CPC分类号： H01J37/32963 ,  H01J37/32935

摘要： A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.

摘要翻译： 一种用于蚀刻薄膜并制造半导体器件的方法包括：在监测从基板远离的端点检测层的移除的同时，对衬底上的薄膜进行蚀刻，从而通过监测薄膜蚀刻来精确控制薄膜蚀刻 移除端点检测层。 端点检测层形成在暴露于与要蚀刻的薄膜相同的蚀刻条件的蚀刻装置的表面上。 当从蚀刻装置的表面去除预定量的端点检测层时，停止对薄膜的蚀刻。

公开(公告)号：US20090068825A1

公开(公告)日：2009-03-12

申请号：US11853156

申请日：2007-09-11

申请人： CHYIU HYIA POON ,  Alex See ,  Mei Sheng Zhou

发明人： CHYIU HYIA POON ,  Alex See ,  Mei Sheng Zhou

IPC分类号： H01L21/22 ,  H01L21/324

CPC分类号： H01L21/324 ,  H01L21/268

摘要： The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.

摘要翻译： 本发明提供了一种通过向半导体结构施加温度相关的相位开关层来退火半导体的方法。 温度相关的相位开关层在预定温度下将相从非晶形变化为结晶。 当半导体结构退火时，电磁辐射在到达半导体结构之前通过温度相关的相位开关层。 当达到期望的退火温度时，温度相关的相位开关层基本上阻止电磁辐射到达半导体结构。 结果，半导体在晶片上以一致的温度退火。 温度相关的相位开关层改变相位的温度可以通过离子注入工艺来控制。

公开(公告)号：US07179879B2

公开(公告)日：2007-02-20

申请号：US11028774

申请日：2005-01-04

申请人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： C08G65/00

CPC分类号： C08G65/40 ,  C08G65/4006 ,  Y10T428/17 ,  Y10T428/31678

摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

摘要翻译： 本发明涉及在电子应用中用作低k电介质层的聚（亚芳基醚）和含有这种聚（亚芳基醚）的制品，其包含以下结构：其中n = 5至10000和一价Ar 1和 二价Ar 2 H 2选自一组包含O，N，Se，S或Te的杂芳族化合物或上述组分的组合，包括但不限于：

公开(公告)号：US07166250B2

公开(公告)日：2007-01-23

申请号：US11028741

申请日：2005-01-04

申请人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： B29C71/00 ,  C08G65/00

CPC分类号： C08G65/40 ,  C08G65/4006 ,  Y10T428/17 ,  Y10T428/31678

摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

公开(公告)号：US20050282396A1

公开(公告)日：2005-12-22

申请号：US10872238

申请日：2004-06-18

申请人： Yu-Liang Lin ,  Henry Lo ,  Chung-Long Chang ,  Gorge Huang ,  Tony Lu ,  Gnesh Yeh ,  Candy Liang ,  Chun-Hsien Lin ,  Mei Sheng Zhou ,  Sunny Wu ,  Ai-Sen Liu ,  Cheng-Lin Huang ,  Li-Jui Chen ,  Shih Wang

发明人： Yu-Liang Lin ,  Henry Lo ,  Chung-Long Chang ,  Gorge Huang ,  Tony Lu ,  Gnesh Yeh ,  Candy Liang ,  Chun-Hsien Lin ,  Mei Sheng Zhou ,  Sunny Wu ,  Ai-Sen Liu ,  Cheng-Lin Huang ,  Li-Jui Chen ,  Shih Wang

IPC分类号： H01L21/00 ,  H01L21/302 ,  H01L21/311 ,  H01L21/336 ,  H01L21/461 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L21/31111 ,  H01L21/67282 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.

摘要翻译： 一种用于局部蚀刻衬底区域的方法和装置，该方法包括提供包含工艺表面的衬底; 在工艺表面上沉积材料层; 以及施加湿蚀刻剂以覆盖所述工艺表面的目标蚀刻部分，同时排除相邻的周围区域以选择性地蚀刻覆盖所述目标蚀刻部分的所述材料层。

公开(公告)号：US06683002B1

公开(公告)日：2004-01-27

申请号：US09636580

申请日：2000-08-10

申请人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Yi Xu

发明人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Yi Xu

IPC分类号： H01L2144

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/31111 ,  H01L21/314 ,  H01L21/76807

摘要： Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

公开(公告)号：US06534393B1

公开(公告)日：2003-03-18

申请号：US09236487

申请日：1999-01-25

申请人： Mei Sheng Zhou ,  Vijai Kumar Chhagan ,  Jian Xun Li

发明人： Mei Sheng Zhou ,  Vijai Kumar Chhagan ,  Jian Xun Li

IPC分类号： H01L214763

CPC分类号： H01L21/76895

摘要： A method for making low sheet resistance local metal interconnections and improved transistor performance is described. The method involves patterning a polysilicon layer and a silicon nitride (Si3N4) cap layer over device areas to form FET gate electrodes, and the patterned polysilicon extends over the field oxide regions to form portions of the local interconnections. After forming source/drain areas and sidewall spacers on the FET gate electrodes, a silicon oxide (SiO2) insulating layer is deposited and polished back to the Si3N4 cap. The Si3N4 is then selectively removed over the patterned polysilicon layer, leaving recesses in the SiO2 layer. After etching contact openings in the SiO2 layer to the substrate, a high electrically conducting metal layer, having a barrier layer, is deposited and patterned to complete the local interconnections. Portions of the metal are retained in the recesses over the pattered polysilicon layer to improve transistor performance, while portions of the metal in the contact openings provide low-contact resistance to the substrate.

摘要翻译： 描述了制造低电阻局部金属互连和改进的晶体管性能的方法。 该方法包括在器件区域上图案化多晶硅层和氮化硅（Si 3 N 4）覆盖层以形成FET栅电极，并且图案化的多晶硅在场氧化物区域上延伸以形成局部互连的部分。 在FET栅电极上形成源极/漏极区域和侧壁间隔物之后，将氧化硅（SiO 2）绝缘层沉积并抛光回Si 3 N 4帽。 然后在图案化的多晶硅层上选择性地去除Si 3 N 4，在SiO 2层中留下凹陷。 在将SiO 2层中的接触开口蚀刻到衬底之后，沉积具有阻挡层的高导电金属层并构图以完成局部互连。 金属的一部分保留在图案化的多晶硅层上的凹槽中以提高晶体管性能，而接触开口中的金属部分提供对基板的低接触电阻。

公开(公告)号：US06530380B1

公开(公告)日：2003-03-11

申请号：US09443428

申请日：1999-11-19

申请人： Mei Sheng Zhou ,  Vincent Sih ,  Simon Chooi ,  Zainab Bte Ismail ,  Ping Yu Ee ,  Sang Yee Loong

发明人： Mei Sheng Zhou ,  Vincent Sih ,  Simon Chooi ,  Zainab Bte Ismail ,  Ping Yu Ee ,  Sang Yee Loong

IPC分类号： H01L21302

CPC分类号： H01L21/31116

摘要： A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may be fabricated, with improved properties and with attenuated degradation. There is first provided a substrate with employed within a microelectronics fabrication having formed thereon patterned microelectronics layers with closely spaced features. There is then formed a salicide block layer employing silicon oxide dielectric material which may be selectively doped. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the patterned photoresist etch mask layer employing dry plasma reactive ion etching. An anhydrous etching environment is then employed to completely remove the silicon oxide dielectric salicide block layer with attenuated degradation of the microelectronics fabrication.

摘要翻译： 用于完全去除在微电子制造中使用的衬底上选择性地形成的介电层的方法，其中可以制造具有改进的性质和衰减劣化的紧密间隔的结构例如自对准金属硅化物（或自对准硅））电接触的区域。 首先提供了在微电子制造中使用的衬底，其中形成有具有紧密间隔的特征的图案化微电子层。 然后形成可以选择性掺杂的氧化硅介电材料的自对准硅化物阻挡层。 然后在衬底上形成图案化的光致抗蚀剂蚀刻掩模层。 然后使用干等离子体反应离子蚀刻蚀刻图案化的光致抗蚀剂蚀刻掩模层的图案。 然后使用无水蚀刻环境以完全去除具有微电子制造的衰减的氧化硅介电硅化物阻挡层。

公开(公告)号：US06461969B1

公开(公告)日：2002-10-08

申请号：US09442314

申请日：1999-11-22

申请人： Pei Ching Lee ,  Wen Jun Liu ,  Mei Sheng Zhou

发明人： Pei Ching Lee ,  Wen Jun Liu ,  Mei Sheng Zhou

IPC分类号： H01L21302

CPC分类号： H01L21/31116

摘要： A method for dry plasma selective etching of a pattern in a silicon nitride dielectric layer formed over a semiconductor substrate employed within a microelectronics fabrication. There is provided a semiconductor substrate having formed thereupon a pad oxide layer over which is formed a silicon nitride dielectric layer. There is formed over the substrate a patterned photoresist etch mask layer. There is then selectively etched the pattern of the photoresist etch mask layer into the silicon nitride layer employing a four-step etching process with three plasma etching environments which include; (1) a “break-through” etching step; (2) a “bulk” etching step to remove a majority of the silicon nitride layer and a “buffer” etching step to remove the remainder of the silicon nitride layer; and (3) an “over-etch” step to complete removal of silicon nitride without excessive etching of underlying material. These steps comprise the selective etching of the patterned silicon nitride layer while maintaining control of critical dimensions, with attenuated microloading and over-etching of underlying material.

摘要翻译： 一种干法等离子体选择性蚀刻形成在微电子学制造中所采用的半导体衬底上的氮化硅介电层中的图案。 提供了在其上形成有氧化硅电介质层的衬垫氧化层形成的半导体衬底。 在衬底上形成图案化的光致抗蚀剂蚀刻掩模层。 然后使用具有三个等离子体蚀刻环境的四步蚀刻工艺将光致抗蚀剂蚀刻掩模层的图案选择性地蚀刻到氮化硅层中，其包括： （1）“突破”蚀刻步骤; （2）去除大部分氮化硅层的“本体”蚀刻步骤和“缓冲”蚀刻步骤以去除其余的氮化硅层; 和（3）“过蚀刻”步骤，以完全去除氮化硅而不过度蚀刻下面的材料。 这些步骤包括对图案化的氮化硅层的选择性蚀刻，同时保持关键尺寸的控制，具有减弱的微负载和对下面的材料的过蚀刻。