公开(公告)号：US07071281B2

公开(公告)日：2006-07-04

申请号：US11028773

申请日：2005-01-04

申请人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： C08G65/00

CPC分类号： C08G65/40 ,  C08G65/4006 ,  Y10T428/17 ,  Y10T428/31678

摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

摘要翻译： 本发明涉及在电子应用中用作低k电介质层的聚（亚芳基醚）和含有这种聚（亚芳基醚）的制品，其包含以下结构：其中n = 5至10000和一价Ar 1和 二价Ar 2 H 2选自一组包含O，N，Se，S或Te的杂芳族化合物或上述组分的组合，包括但不限于：

公开(公告)号：US06846899B2

公开(公告)日：2005-01-25

申请号：US10262144

申请日：2002-10-01

申请人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： C08G65/40 ,  H01L21/312 ,  H01L21/768 ,  C08G65/00

CPC分类号： C08G65/40 ,  C08G65/4006 ,  Y10T428/17 ,  Y10T428/31678

摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

摘要翻译： 本发明涉及在电子应用中用作低k电介质层的聚（亚芳基醚）和含有这种聚（亚芳基醚）的制品，其包含以下结构：其中n = 5至10000，一价Ar 1和二价Ar 2选自 包含O，N，Se，S或Te的杂芳族化合物或上述元素的组合，包括但不限于：

公开(公告)号：US07179879B2

公开(公告)日：2007-02-20

申请号：US11028774

申请日：2005-01-04

申请人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： C08G65/00

CPC分类号： C08G65/40 ,  C08G65/4006 ,  Y10T428/17 ,  Y10T428/31678

摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

摘要翻译： 本发明涉及在电子应用中用作低k电介质层的聚（亚芳基醚）和含有这种聚（亚芳基醚）的制品，其包含以下结构：其中n = 5至10000和一价Ar 1和 二价Ar 2 H 2选自一组包含O，N，Se，S或Te的杂芳族化合物或上述组分的组合，包括但不限于：

公开(公告)号：US07166250B2

公开(公告)日：2007-01-23

申请号：US11028741

申请日：2005-01-04

申请人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Christopher Lim ,  Siu Choon Ng ,  Hardy Chan ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： B29C71/00 ,  C08G65/00

CPC分类号： C08G65/40 ,  C08G65/4006 ,  Y10T428/17 ,  Y10T428/31678

摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

公开(公告)号：US06987321B2

公开(公告)日：2006-01-17

申请号：US10718865

申请日：2003-11-21

申请人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subbash Gupta ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Yi Xu

发明人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subbash Gupta ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Yi Xu

IPC分类号： H01L23/48

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/31111 ,  H01L21/314 ,  H01L21/76807

摘要： Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

摘要翻译： 用于形成双镶嵌互连结构的方法和产品，其中将铜硫化物界面层作为开口的侧壁沉积阻止铜离子迁移或扩散到电介质材料中。

公开(公告)号：US06705512B2

公开(公告)日：2004-03-16

申请号：US10099283

申请日：2002-03-15

申请人： Kwok Keung Paul Ho ,  Simon Chooi ,  Yi Xu ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy

发明人： Kwok Keung Paul Ho ,  Simon Chooi ,  Yi Xu ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy

IPC分类号： B23K3102

CPC分类号： H01L24/85 ,  B23K20/007 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/04953 ,  H01L2224/78 ,  H01L2924/00

摘要： A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.

摘要翻译： 将接合元件接合到金属接合焊盘的方法包括以下步骤。 提供了一种在层开口内具有暴露的凹陷金属接合焊盘的半导体结构。 该层具有上表面。 在金属焊盘上形成具有预定厚度的导电盖。 接合元件结合到导电盖以与金属接合焊盘形成电连接。

公开(公告)号：US06565664B2

公开(公告)日：2003-05-20

申请号：US10131519

申请日：2002-04-24

申请人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

IPC分类号： C23G114

CPC分类号： H01L21/32134 ,  C23F1/34 ,  H01L21/7684 ,  Y10S134/902

摘要： An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

公开(公告)号：US06524910B1

公开(公告)日：2003-02-25

申请号：US09670329

申请日：2000-09-27

申请人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

发明人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/31662 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.

摘要翻译： 已经开发了一种用于形成第一组栅极结构的工艺，其设计成在比同时形成的第二组栅极结构低的电压下工作。 该方法的特征在于在用于低电压栅极结构的半导体衬底的一部分上的第一二氧化硅栅极绝缘体层的热生长，同时在所使用的半导体衬底的一部分上形成较厚的第二二氧化硅栅极绝缘体层 对于较高电压门结构。 第一和第二二氧化硅栅极绝缘体层的热生长通过氧化物质的扩散来实现：通过厚的复合氮化硅层，以获得较薄的第一二氧化硅栅极绝缘体层，在第一部分 半导体衬底; 并通过较薄的氮化硅层，以在半导体衬底的第二部分上获得较厚的第二二氧化硅栅极绝缘体层。

公开(公告)号：US06479383B1

公开(公告)日：2002-11-12

申请号：US10068823

申请日：2002-02-05

申请人： Simon Chooi ,  Mei Sheng Zhou

发明人： Simon Chooi ,  Mei Sheng Zhou

IPC分类号： H01L2144

CPC分类号： H01L21/32134 ,  H01L21/28518 ,  H01L21/321

摘要： A method to remove a metal from over a substrate in the fabrication of an integrated circuit device. The invention comprises providing a metal layer over a substrate. The metal layer is exposed to a reactant gas to form at least a solid metal containing product. The reactant gas preferably contains sulfur and oxygen. The reactant gas more preferably comprises sulfur dioxide or sulfur trioxide. The reactant gas is preferably heated and optionally exposed to a plasma. Next, the metal containing product is removed using a liquid, thereby removing at least portion of the metal layer from over the substrate.

摘要翻译： 一种在制造集成电路器件中从衬底上去除金属的方法。 本发明包括在衬底上提供金属层。 金属层暴露于反应气体中以形成至少含固体金属的产品。 反应气体优选含有硫和氧。 反应气体更优选包含二氧化硫或三氧化硫。 反应气体优选被加热并任选地暴露于等离子体。 接下来，使用液体除去含金属的产品，从而从基板上除去金属层的至少一部分。

公开(公告)号：US06429129B1

公开(公告)日：2002-08-06

申请号：US09594415

申请日：2000-06-16

申请人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

发明人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.