公开(公告)号：US07881385B2

公开(公告)日：2011-02-01

申请号：US11015555

申请日：2004-12-17

Applicant: Alexander G. MacInnis ,  Jose' R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose' R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/18

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。

公开(公告)号：US07877752B2

公开(公告)日：2011-01-25

申请号：US11300610

申请日：2005-12-14

Applicant: Darren Neuman

Inventor： Darren Neuman

IPC: G06F9/46 ,  G06F3/00 ,  G06F17/00 ,  G06F15/16 ,  G09G5/399

CPC classification number: G06F9/4887 ,  H04N21/23406 ,  H04N21/44004

Abstract: Methods and systems for coordinating the handling of information are disclosed herein and may include scheduling multiple processing tasks for processing multimedia data by a processor. A portion of the scheduled multiple processing tasks may be preprocessed and the preprocessed portion may be buffered within a modifiable buffer that handles overflow and underflow. A portion of the buffered preprocessed portion of the scheduled multiple processing tasks may be executed. The scheduling may utilize a non-preemptive scheduling algorithm, such as an earliest deadline first (EDF) scheduling algorithm and/or a rate monotonic (RM) scheduling algorithm. The scheduled multiple processing tasks may include at least one maximum real deadline. The preprocessed portion of the scheduled multiple processing tasks may be outputted during processing of the blocking task, if a current task of the scheduled multiple processing tasks comprises a blocking task.

Abstract translation: 用于协调信息处理的方法和系统在此公开，并且可以包括调度处理器处理多媒体数据的多个处理任务。 调度的多个处理任务的一部分可以被预处理，并且预处理部分可以在处理溢出和下溢的可修改缓冲器内被缓冲。 调度的多个处理任务的缓冲预处理部分的一部分可以被执行。 调度可以利用非优先调度算法，例如最早的最终期限（EDF）调度算法和/或速率单调（RM）调度算法。 预定的多个处理任务可以包括至少一个最大实际截止日期。 如果调度的多个处理任务的当前任务包括阻塞任务，则可以在处理阻塞任务期间输出所调度的多个处理任务的预处理部分。

公开(公告)号：US07864806B2

公开(公告)日：2011-01-04

申请号：US10752336

申请日：2004-01-06

Applicant: Jack Qiu ,  Jonathan Lee

Inventor： Jack Qiu ,  Jonathan Lee

IPC: H04J3/24

CPC classification number: H04L69/16 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9042 ,  H04L69/12 ,  H04L69/166 ,  H04L69/326

Abstract: Certain aspects of the invention for packet segmentation and offload may comprise determining whether an identified packet is a large send offload packet (LSOP). If the identified packet is a LSOP, a selection may be made between a hardware process and a firmware process for handling the LSOP. The LSOP may then be processed by the selected hardware process or firmware process. At least a portion of protocol header information for a first segment of the LSOP may be stored and subsequently utilized for at least a header portion of a second segment of the LSOP. A payload corresponding to the second segment of the LSOP may be placed at a determined offset within a transmit buffer for the second segment. A header portion of the second segment may be updated based on at least a header portion of a previous segment.

Abstract translation: 用于分组分段和卸载的本发明的某些方面可以包括确定所识别的分组是否是大的发送卸载分组（LSOP）。 如果识别的分组是LSOP，则可以在硬件处理和用于处理LSOP的固件处理之间进行选择。 然后可以通过所选择的硬件过程或固件处理来处理LSOP。 用于LSOP的第一段的协议报头信息的至少一部分可以被存储并随后用于LSOP的第二段的至少一个报头部分。 可以将对应于LSOP的第二段的有效载荷置于第二段的发送缓冲器内的确定的偏移处。 可以基于至少前一段的报头部分来更新第二段的报头部分。

公开(公告)号：US07853254B2

公开(公告)日：2010-12-14

申请号：US12132363

申请日：2008-06-03

Applicant: Steven E. Koenck ,  Phillip Miller ,  Guy J. West ,  Ronald L. Mahany ,  Patrick W. Kinney

Inventor： Steven E. Koenck ,  Phillip Miller ,  Guy J. West ,  Ronald L. Mahany ,  Patrick W. Kinney

IPC: H04W4/00

CPC classification number: G06F1/32 ,  H04W52/0261 ,  H04W88/02 ,  Y02D70/00

Abstract: Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter modules and associated antennas may be selectively added to a base terminal unit to solve networking problems associated with specific types of business environments. Modularity exists in both the hardware (splitting data collection and processing control circuitry from radio transceiver control circuitry) and software (splitting transceiver-specific, lower level communication protocol from generic, higher level communication protocol). The control circuitry, including associated microprocessors devices, interact to selectively activate communication circuits to perform necessary communication or data processing functions and enter and remain in a power-saving dormant state during other times. To support such dormant or “sleeping” states, a series of communication protocols provide for channel access to the communication network. The disclosed modular design also provides for automatic selection from a variety of available built-in and externally mounted antennas based on the particular type of radio transceiver(s) selected.

Abstract translation: 公开了用于混合无线和硬连线RF通信网络中的模块化便携式数据收集终端，其中可以将各种无线电发射机模块和相关天线选择性地添加到基站终端单元以解决与特定类型的业务环境相关联的网络问题。 模块化存在于硬件（分配来自无线电收发器控制电路的数据收集和处理控制电路）和软件（从通用，更高级别的通信协议中分离收发器特定的较低级别的通信协议）。 包括相关联的微处理器设备的控制电路相互作用以选择性地激活通信电路以执行必要的通信或数据处理功能，并且在其它时间进入并保持在省电休眠状态。 为了支持这种休眠或“睡眠”状态，一系列通信协议提供对通信网络的信道接入。 所公开的模块化设计还提供了基于所选择的无线电收发器的特定类型的各种可用的内置和外部安装天线的自动选择。

公开(公告)号：US07826550B2

公开(公告)日：2010-11-02

申请号：US11680370

申请日：2007-02-28

Applicant: Ahmadreza Rofougaran

Inventor： Ahmadreza Rofougaran

IPC: H03K7/06 ,  H03K9/06

CPC classification number: H04L27/361 ,  H03L7/18 ,  H04L27/2627 ,  H04L27/2649

Abstract: Aspects of a method and system for a high-precision frequency generator using a direct digital frequency synthesizer for transmitters and receivers may include generating a second signal from a first signal by frequency translating an inphase component of the first signal utilizing a high-precision oscillating signal that may be generated using at least a direct digital frequency synthesizer (DDFS) and at least a Phase-Locked Loop (PLL). A corresponding quadrature component of the first signal may be frequency translated utilizing a phase-shifted version of the high-precision oscillating signal. The inphase component of the first signal may be multiplied with the high-precision oscillating signal and the quadrature component of the first signal may be multiplied with the phase-shifted version of the high-precision oscillating signal. The second signal may be generated from the first signal by adding the frequency translated inphase component to the frequency translated quadrature component.

Abstract translation: 使用用于发射机和接收机的直接数字频率合成器的高精度频率发生器的方法和系统的方面可以包括通过使用高精度振荡信号频率转换第一信号的同相分量来从第一信号产生第二信号 这可以使用至少一个直接数字频率合成器（DDFS）和至少一个锁相环（PLL）产生。 第一信号的对应正交分量可以利用高精度振荡信号的相移版本进行频率转换。 第一信号的同相分量可以与高精度振荡信号相乘，并且第一信号的正交分量可以与高精度振荡信号的相移版本相乘。 可以通过将频率转换的同相分量相加到频率转换正交分量从第一信号生成第二信号。

公开(公告)号：US07802308B2

公开(公告)日：2010-09-21

申请号：US11868146

申请日：2007-10-05

Applicant: Marcus Kellerman ,  Jeyhan Karaoguz ,  James D. Bennett

Inventor： Marcus Kellerman ,  Jeyhan Karaoguz ,  James D. Bennett

IPC: G06F15/16 ,  G06F21/00

CPC classification number: H04L29/08756 ,  H04L12/2803 ,  H04L12/2834 ,  H04L29/06027 ,  H04L65/1069 ,  H04L65/1073 ,  H04L65/4076 ,  H04L65/4084 ,  H04L65/605 ,  H04L67/06 ,  H04L67/2823 ,  H04L67/306 ,  H04L67/325 ,  H04L67/327 ,  H04L2012/2841 ,  H04L2012/2849 ,  H04N7/141 ,  H04N7/163 ,  H04N7/18 ,  H04N21/2343 ,  H04N21/234363 ,  H04N21/2408 ,  H04N21/254 ,  H04N21/2541 ,  H04N21/2543 ,  H04N21/25435 ,  H04N21/25833 ,  H04N21/25875 ,  H04N21/26266 ,  H04N21/2668 ,  H04N21/2743 ,  H04N21/4126 ,  H04N21/41422 ,  H04N21/4227 ,  H04N21/42684 ,  H04N21/4316 ,  H04N21/4331 ,  H04N21/43615 ,  H04N21/43637 ,  H04N21/44222 ,  H04N21/4532 ,  H04N21/458 ,  H04N21/4622 ,  H04N21/4627 ,  H04N21/4668 ,  H04N21/47214 ,  H04N21/4751 ,  H04N21/4755 ,  H04N21/4788 ,  H04N21/482 ,  H04N21/4821 ,  H04N21/4826 ,  H04N21/4882 ,  H04N21/6125 ,  H04N21/6187 ,  H04N21/632 ,  H04N21/6582 ,  H04N21/6583 ,  H04N21/814 ,  H04N21/8146

Abstract: Methods and systems for processing media content are disclosed and may include a server operatively coupled to a network, a first communications device operatively coupled to the network, and a second communications device operatively coupled to the network. The second communications device may receive, from the first communications device, a device profile relating to the first communications device. The second communications device may send the device profile, received from the first communications device, and media content to the server. The server may reformat the media content based on the device profile received from the first communications device. The server may send the reformatted media content to the first communications device. The server may transcode the media content from a first type of format to a second type of format. The second type of format may be compatible with the first communications device.

Abstract translation: 公开了用于处理媒体内容的方法和系统，并且可以包括可操作地耦合到网络的服务器，可操作地耦合到网络的第一通信设备和可操作地耦合到网络的第二通信设备。 第二通信设备可以从第一通信设备接收与第一通信设备相关的设备简档。 第二通信设备可以将从第一通信设备接收的设备简档和媒体内容发送到服务器。 服务器可以基于从第一通信设备接收的设备简档重新格式化媒体内容。 服务器可以将重新格式化的媒体内容发送到第一通信设备。 服务器可以将媒体内容从第一类型的格式转码为第二类型的格式。 第二类型的格式可以与第一通信设备兼容。

公开(公告)号：US07728866B2

公开(公告)日：2010-06-01

申请号：US11266448

申请日：2005-11-03

Applicant: Bruce J. Currivan ,  Xuemin Chen

Inventor： Bruce J. Currivan ,  Xuemin Chen

IPC: H04N7/14 ,  G06K9/00

CPC classification number: H04N7/14 ,  H04N7/147 ,  H04N7/157

Abstract: Herein described is a system and method for modifying facial video transmitted from a first videophone to a second videophone during a videophone conversation. A videophone comprises a videophone image processing system (VIPS) that stores one or more preferred images. The one or more preferred images may comprise an image of a person presented in an attractive appearance. The one or more preferred images may comprise one or more avatars. Additionally, the VIPS may be used to incorporate one or more facial features of the person into a preferred image or avatar. Furthermore, a replacement background may be incorporated into the preferred image or avatar. The VIPS transmits a preferred image of a first speaker of a first videophone to a second speaker of a second videophone by capturing an actual image of the first speaker and substituting at least a portion of said actual image with a stored image.

Abstract translation: 这里描述了一种用于在视频电话会话期间修改从第一可视电话传输到第二可视电话的面部视频的系统和方法。 视频电话包括存储一个或多个优选图像的可视电话图像处理系统（VIPS）。 一个或多个优选图像可以包括呈现在有吸引力的外观中的人​​的图像。 一个或多个优选图像可以包括一个或多个化身。 此外，VIPS可以用于将该人的一个或多个面部特征并入优选图像或化身。 此外，替换背景可以并入优选图像或化身。 VIPS通过捕获第一扬声器的实际图像并用存储的图像代替所述实际图像的至少一部分来将第一可视电话的第一扬声器的优选图像发送到第二可视电话的第二扬声器。

公开(公告)号：US07724682B2

公开(公告)日：2010-05-25

申请号：US11333811

申请日：2006-01-17

Applicant: Branko D. Kovacevic

Inventor： Branko D. Kovacevic

IPC: H04L12/28 ,  H04J1/00 ,  H04J3/07 ,  G06F15/16 ,  G06F15/167

CPC classification number: H04N21/23424 ,  H04N21/44016

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream. In another embodiment, the hardware is used to implement a splicing of streams of data. A method and system for generating a transport stream for testing such a system is disclosed using a data record specifying a packetized elementary stream payload portion, a transport packet portion, and an adaptation field portion. A text data record is used to generate specific transport stream data to test demultiplexer systems.

Abstract translation: 根据本发明的具体方面，诸如MPEG-2视频流的压缩视频流由传输解复用器接收，被同步，被解析成单独的分组类型，并被写入到解复用器外部的缓冲器位置。 适应字段由单独的解析器处理。 此外，主基本流数据可以基于主基本流的分组标识符由单独的主要基本流解析器来处理。 视频数据包可以基于流标识符值进行解析。 基于分配表信息，通过输出控制器将特定数据分组存储在一个或多个系统存储器或视频存储器缓冲器中。 与特定基本流或分组适配字段相关联的私有数据被重新分组，并被写入输出缓冲器位置。 在具体实现中，与系统相关联的硬件用于获取数据流，而不知道流的特定协议。 在另一个实施例中，硬件用于实现数据流的拼接。 使用指定分组化的基本流有效载荷部分，传输分组部分和适配字段部分的数据记录来公开用于生成用于测试这样的系统的传输流的方法和系统。 文本数据记录用于生成特定的传输流数据以测试多路分解器系统。

公开(公告)号：US07607052B2

公开(公告)日：2009-10-20

申请号：US10997598

申请日：2004-11-23

Applicant: John L. Creigh

Inventor： John L. Creigh

IPC: G06F11/00

CPC classification number: G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/32 ,  H04L1/0054 ,  H04L1/242 ,  H04L7/0062 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

Abstract: A physical coding sublayer (PCS) transmitter circuit generates a plurality of encoded symbols according to a transmission standard. A symbol skewer skews the plurality of encoded symbols within a symbol clock time. A physical coding sublayer (PCS) receiver core circuit decodes a plurality of symbols based on encoding parameters. The symbols are transmitted using the encoding parameters according to a transmission standard. The received symbols are skewed within a symbol clock time by respective skew intervals. A PCS receiver encoder generator generates the encoding parameters.

Abstract translation: 物理编码子层（PCS）发送器电路根据传输标准产生多个编码符号。 符号串在符号时钟时间内偏移多个编码符号。 物理编码子层（PCS）接收机核心电路基于编码参数解码多个符号。 使用编码参数根据传输标准传输符号。 接收到的符号在符号时钟时间内偏斜相应的偏移间隔。 PCS接收机编码器生成器生成编码参数。

公开(公告)号：US07596144B2

公开(公告)日：2009-09-29

申请号：US11228363

申请日：2005-09-16

Applicant: Fong Pong

Inventor： Fong Pong

IPC: H04J3/16 ,  H04J3/22 ,  G06F15/76

CPC classification number: H04L69/08 ,  H04L69/16 ,  H04L69/165

Abstract: Certain aspects of a method and system for a system-on-a-chip (SoC) device with integrated support for Ethernet, TCP, iSCSI, RDMA, and network application acceleration are provided. Aspects of the method may include storing on a multifunction host bus adapter (MHBA) chip that handles a plurality of protocols, at least a portion of received data for at least one of a plurality of network connections. The MHBA chip may be configured for handling the received data based on one of the plurality of protocols that is associated with the received data. The received data for the at least one of the plurality of network connections may be processed within the MHBA chip. The one of the plurality of protocols may include an Ethernet protocol, a transmission control protocol (TCP), an Internet protocol (IP), an Internet small computer system interface (iSCSI) protocol, and/or a remote direct memory access (RDMA) protocol.

Abstract translation: 提供了一种集成支持以太网，TCP，iSCSI，RDMA和网络应用加速的片上系统（SoC）设备的方法和系统的某些方面。 该方法的方面可以包括存储在处理多个协议的多功能主机总线适配器（MHBA）芯片上，用于多个网络连接中的至少一个的接收数据的至少一部分。 MHBA芯片可以被配置为基于与所接收的数据相关联的多个协议之一来处理接收到的数据。 可以在MHBA芯片内对多个网络连接中的至少一个网络连接的接收数据进行处理。 多个协议之一可以包括以太网协议，传输控制协议（TCP），因特网协议（IP），因特网小型计算机系统接口（iSCSI）协议和/或远程直接存储器访问（RDMA） 协议。