公开(公告)号：US20230185714A1

公开(公告)日：2023-06-15

申请号：US17547686

申请日：2021-12-10

Applicant: SAP SE

Inventor： Roland Sedler ,  Umang Rawat ,  Matthias Hauck ,  Hannes Jakschitsch ,  Daniel Ritter

IPC: G06F12/0802 ,  G06F16/901

CPC classification number: G06F12/0802 ,  G06F16/9024 ,  G06F2212/60

Abstract: A method may include accessing a cache storing a graph index corresponding to a graph data in response to a transaction operating on the graph data. A cache miss triggered by a change to the underlying graph data may be detected. In response to detecting the cache miss, the graph index may be updated by at least replaying or rewinding one or more other changes made to the graph data by one or more other transactions between a first time of the transaction and a second time of a current version of the graph index in the cache. The graph index may be updated to avoid a full rebuild of the graph index. The transaction may be executed based on the updated graph index. Related systems and computer program products are also provided.

公开(公告)号：US11670416B2

公开(公告)日：2023-06-06

申请号：US17447560

申请日：2021-09-13

Applicant: ICU Medical, Inc.

Inventor： Ben Xavier ,  Dennis Krabbe ,  Larry Enger

IPC: G16H40/20 ,  G16H20/17 ,  G06F12/0802 ,  G16H40/40 ,  A61M5/172 ,  H04L29/08 ,  H04L29/06 ,  G16H40/67 ,  G16H40/63 ,  A61M5/142 ,  G16H40/60 ,  G16H80/00 ,  H04L67/565 ,  H04L9/40 ,  H04L67/125 ,  H04L67/00 ,  H04L69/08 ,  H04L69/18 ,  G06F16/2455 ,  H04L67/5682 ,  H04L43/0811 ,  H04L43/16 ,  H04L67/10

CPC classification number: G16H40/20 ,  A61M5/142 ,  A61M5/172 ,  G06F12/0802 ,  G06F16/24552 ,  G16H20/17 ,  G16H40/40 ,  G16H40/60 ,  G16H40/63 ,  G16H40/67 ,  G16H80/00 ,  H04L43/0811 ,  H04L43/16 ,  H04L63/08 ,  H04L67/125 ,  H04L67/34 ,  H04L67/565 ,  H04L67/5682 ,  H04L69/08 ,  H04L69/18 ,  A61M2005/14208 ,  A61M2205/18 ,  A61M2205/3553 ,  A61M2205/3561 ,  A61M2205/3584 ,  A61M2205/3592 ,  A61M2205/52 ,  H04L67/10

Abstract: Various techniques for facilitating communication with and across a clinical environment and a cloud environment are described. For example, a method for tagging messages with facility identifiers in a manner that does not require changing the identifiers when logically re-arranging the facilities. A connectivity adapter in the clinical environment can receive a message from an infusion pump and tag the message with only permanent IDs such that when the facility in which the connectivity resides is categorized under a different system or region, the identifiers in the message need not be updated.

公开(公告)号：US11669449B1

公开(公告)日：2023-06-06

申请号：US17457000

申请日：2021-11-30

Applicant: Dell Products L.P.

Inventor： Keyur B. Desai ,  Xiaobing Zhang

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: One example method includes a cache eviction operation. Entries in a cache are maintained in an entry list that includes a recent list, a recent ghost list, a frequent list, and a frequent ghost list. When an eviction operation is initiated or triggered, timestamps of last access for the entries in the entry list are adjusted by corresponding adjustment values. Candidate entries for eviction are identified based on the adjusted timestamps of last access. At least some of the candidates are evicted from the cache.

公开(公告)号：US11657185B2

公开(公告)日：2023-05-23

申请号：US17559484

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello

IPC: G06F21/74 ,  G06F12/0802 ,  G06F12/14 ,  G06F21/30 ,  G06F21/79 ,  G11C5/06 ,  G06F13/16 ,  G11C16/04

CPC classification number: G06F21/74 ,  G06F12/0802 ,  G06F12/14 ,  G06F21/30

Abstract: Methods, systems, and devices for a memory access gate are described. A memory device may include a controller, memory dice, and a pad for receiving an externally provided control signal, such as a chip enable signal. The memory device may include a switching component for selecting the externally provided control signal or an internally generated control signal. The controller may provide the selected control signal to a memory die. The memory device may determine whether it is operating in a first mode or a second mode, and select the externally provided control signal or the internally generated control signal based on the determination. The first mode may be a diagnostic mode in some cases. The controller may include a secure register whose value may impact or control the switching. An authenticated host device may direct the controller to write the value to the secure register.

公开(公告)号：US11656992B2

公开(公告)日：2023-05-23

申请号：US16548116

申请日：2019-08-22

Applicant: Western Digital Technologies, Inc.

Inventor： Marjan Radi ,  Dejan Vucinic

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0806 ,  G06F12/0802 ,  H04L67/1097 ,  G06F12/0817 ,  H04L67/568 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F12/0862 ,  G06F12/0802 ,  G06F12/082 ,  G06F12/0806 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0828 ,  H04L67/1097 ,  H04L67/568 ,  G06F9/34 ,  G06F9/3824 ,  G06F2212/154 ,  G06F2212/602

Abstract: A programmable switch receives a cache line request from a client of a plurality of clients on a network to obtain a cache line. One or more additional cache lines are identified based on the received cache line request and prefetch information. The cache line and the one or more additional cache lines are requested from one or more memory devices on the network. The requested cache line and the one or more additional cache lines are received from the one or more memory devices, and are sent to the client.

公开(公告)号：US11656801B2

公开(公告)日：2023-05-23

申请号：US17736806

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Shanky Kumar Jain ,  Dmitri A. Yudanov

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/109 ,  G11C7/1012 ,  G11C7/1063 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/40603 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

公开(公告)号：US11650918B2

公开(公告)日：2023-05-16

申请号：US17528664

申请日：2021-11-17

Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Dong Kun Shin ,  Gyeong Hwan Hong

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/608

Abstract: A method of compressing an address includes receiving an input of a full address including a first part and a second part; checking a segment base address based on the first part in a previously stored reverse map cache (RMC); obtaining a block offset based on the segment base address and the second part; and outputting a compressed address by compressing the first part and the second part, respectively, based on the segment base address and the block offset.

公开(公告)号：US20230145267A1

公开(公告)日：2023-05-11

申请号：US17932247

申请日：2022-09-14

Applicant: ICU Medical, Inc.

Inventor： Ben Xavier ,  Dennis Krabbe ,  Larry Enger ,  Chaitanya Deosthale ,  Anthony Isensee

IPC: H04L67/00 ,  G16H40/60 ,  G16H80/00 ,  G06F12/0802 ,  G16H40/40 ,  A61M5/172 ,  H04L67/125 ,  H04L9/40 ,  G16H40/67 ,  G16H40/63 ,  H04L69/18 ,  G06F16/2455 ,  H04L67/5682 ,  H04L43/0811 ,  H04L43/16

CPC classification number: H04L67/34 ,  A61M5/172 ,  G06F12/0802 ,  G06F16/24552 ,  G16H40/40 ,  G16H40/60 ,  G16H40/63 ,  G16H40/67 ,  G16H80/00 ,  H04L43/16 ,  H04L43/0811 ,  H04L63/08 ,  H04L67/125 ,  H04L67/5682 ,  H04L69/18 ,  G16H20/17

Abstract: Various techniques for facilitating communication with and across a clinical environment and a cloud environment are described. For example, a method for providing messaging in a clinical environment during a network outage is described. During a network outage, messages in the queue may become stale. A connectivity adapter may remove those messages from the queue. When the network connection is restored, the connectivity adapter may transmit any remaining messages in the queue.

公开(公告)号：US20230143829A1

公开(公告)日：2023-05-11

申请号：US17965004

申请日：2022-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Min-Hwi Kim ,  Makoto Hirano

IPC: G11C16/24 ,  G06F12/0802

CPC classification number: G11C16/24 ,  G06F12/0802 ,  G11C16/0483

Abstract: A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.

公开(公告)号：US20190235611A1

公开(公告)日：2019-08-01

申请号：US16382320

申请日：2019-04-12

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/3234 ,  G06F12/0802 ,  G06F12/0864 ,  G06F1/28 ,  G06F12/084 ,  G06F1/3287 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.