利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

646 条记录 (耗时 0.014 秒)

    Method of fabricating an insulated gate field effect device
    91.
    发明授权
    Method of fabricating an insulated gate field effect device 失效
    制造绝缘栅场效应器件的方法

    公开(公告)号：US4181537A

    公开(公告)日：1980-01-01

    申请号：US805576

    申请日：1977-06-10

    申请人： Eisuke Ichinohe

    发明人： Eisuke Ichinohe

    IPC分类号： H01L29/78 ,  H01L21/033 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01G7/00 ,  H01L7/44 ,  H01L11/14 ,  H01L29/04

    CPC分类号： H01L29/66575 ,  H01L21/033 ,  H01L21/76202 ,  H01L29/41783

    摘要： This invention provides a method of making an improved gate structure in which the gate electrode is self-aligned with respect to the field isolation oxide regions.Gate constituting layers are formed on a substrate prior to formation of the field isolation oxide regions. An oxidation barrier layer is provided on such layers, also covering the other regions which should be formed into the source and drain regions, etc. By etching off the oxidation barrier layer above the field isolation regions, the boundary edges of the gate on the field isolation regions are formed. Then oxidation is performed using the oxidation barrier as a masking pattern to form the field isolation oxide regions. The field isolation oxide regions and the gate thus formed completely coincide with each other at their boundary edges.

    摘要翻译： 本发明提供一种制造栅极结构的改进方法，其中栅电极相对于场隔离氧化物区域自对准。 在形成场隔离氧化物区域之前，在衬底上形成栅极构成层。 在这样的层上设置有氧化阻挡层，也覆盖应形成源极和漏极区域的其它区域等。通过在场隔离区域上蚀刻氧化阻挡层，场上栅极的边界边缘 形成隔离区。 然后使用氧化屏障进行氧化作为掩模图案以形成场隔离氧化物区域。 这样形成的场隔离氧化物区域和栅极在其边界边缘处完全相互重合。

    Laser trim protection process
    92.
    发明授权
    Laser trim protection process 失效
    激光调整保护过程

    公开(公告)号：US4179310A

    公开(公告)日：1979-12-18

    申请号：US921743

    申请日：1978-07-03

    申请人： James B. Compton ,  Robert A. Cometta ,  Daniel D. Culmer

    发明人： James B. Compton ,  Robert A. Cometta ,  Daniel D. Culmer

    IPC分类号： H01L21/033 ,  H01L21/268 ,  B23K27/00

    CPC分类号： H01L21/033 ,  H01L21/268 ,  Y10S148/092 ,  Y10S148/093 ,  Y10S438/94

    摘要： An element of an integrated circuit, such as an ion implanted region or a metal layer, may be laser trimmed without exposing P-N junctions or other circuit elements not to be trimmed to damage by the laser through use of the present protection process and structure. In the process, an oxide through which the laser trimming is carried out is formed over a selected portion of the circuit to be trimmed by the laser. A bare layer of a metal reflective to the laser radiant energy beam, such as aluminum, gold or silver, is formed surrounding the selected portion of the circuit. The selected portion of the integrated circuit is then trimmed with the laser. The oxide promotes trimming in the selected area by absorbing the laser radiant energy beam. The bare metal layer protects the portion of the integrated circuit underlying it by reflecting most of its energy.

    摘要翻译： 诸如离子注入区域或金属层的集成电路的元件可以被激光修整，而不会通过使用本保护过程和结构暴露P-N结或不被修整的其它电路元件以被激光损坏。 在该过程中，通过激光修整的电路的选定部分上形成进行激光微调的氧化物。 在电路的选定部分周围形成反射到激光辐射能量束（例如铝，金或银）的裸金属的裸露层。 然后用激光器对该集成电路的选定部分进行修整。 氧化物通过吸收激光辐射能量束促进所选区域的修整。 裸金属层通过反映其大部分能量来保护其下面的集成电路的部分。

    Method for covering a first layer or layer sequence situated on a substrate with an additional second layer by a sputtering-on process
    93.
    发明授权
    Method for covering a first layer or layer sequence situated on a substrate with an additional second layer by a sputtering-on process 失效
    通过溅射工艺用另外的第二层覆盖位于衬底上的第一层或层序列的方法

    公开(公告)号：US4162210A

    公开(公告)日：1979-07-24

    申请号：US872433

    申请日：1978-01-26

    申请人： Hans-Raimund Deppe

    发明人： Hans-Raimund Deppe

    IPC分类号： H01L21/203 ,  C23C14/34 ,  H01L21/033 ,  H01L21/311 ,  H01L21/316 ,  H01L21/3213 ,  C23C15/00

    CPC分类号： C23C14/345 ,  C23C14/34 ,  H01L21/02164 ,  H01L21/02266 ,  H01L21/033 ,  H01L21/31105 ,  H01L21/31612 ,  H01L21/32132

    摘要： A method is disclosed for eliminating under-etchings. In a substrate having a lower silicon dioxide layer thereon, a polysilicon layer on the silicon dioxide layer, and an upper silicon dioxide layer on the polysilicon layer, an etched window provided in the layers has first under-etchings formed at an edge of the lower silicon dioxide layer adjacent the substrate and a second under-etching formed at an edge of the polysilicon layer. A sputtering source is provided with a given target voltage. A grid potential is applied to the substrate wherein the grid potential is between one-tenth and one-third of the target voltage. A layer is then sputter deposited in the etching window for filling in the first under-etching by re-emission from the surface of the substrate and for sloping the edge of the polysilicon layer at the second under-etching. An overhanging portion of the upper silicon dioxide layer is also removed at the second under-etching by re-emission during the sputter deposition.

    摘要翻译： 公开了一种消除欠蚀刻的方法。 在其上具有较低二氧化硅层的衬底中，二氧化硅层上的多晶硅层和多晶硅层上的上二氧化硅层，设置在该层中的蚀刻窗口具有形成在下层的边缘处的第一底蚀刻 邻近衬底的二氧化硅层和在多晶硅层的边缘处形成的第二次蚀刻。 溅射源具有给定的目标电压。 栅极电位施加到基板，其中栅极电位在目标电压的十分之一到三分之一之间。 然后在蚀刻窗口中溅射沉积一层，用于通过从衬底的表面再发射并在第二次蚀刻下倾斜多晶硅层的边缘来填充第一次蚀刻。 在溅射沉积期间通过再发射在第二次蚀刻下也去除上部二氧化硅层的悬垂部分。

    Method of manufacturing self-aligned semiconductor devices
    94.
    发明授权
    Method of manufacturing self-aligned semiconductor devices 失效
    制造自对准半导体器件的方法

    公开(公告)号：US4131497A

    公开(公告)日：1978-12-26

    申请号：US814829

    申请日：1977-07-12

    申请人： Bai-Cwo Feng ,  George C. Feng

    发明人： Bai-Cwo Feng ,  George C. Feng

    IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/31 ,  H01L21/314 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/265

    CPC分类号： H01L21/3144 ,  H01L21/033 ,  H01L21/8222

    摘要： A method of forming extremely small impurity regions within other impurity regions without the need for providing critical masks. In the preferred embodiment this is achieved by forming an undercut band within masking layers atop a substrate to define a first impurity region, such as the base region of a bipolar transistor. After this region is formed by the introduction of impurities, the undercut is filled-in by a chemical vapor deposition process. A blocking mask may then be used for the formation of the second impurity region, in this case the emitter, within the first region. The window of the second region is defined by the filled-in band, thereby insuring a selected distance between the peripheries of said first and second impurity regions. The same mask may also be used to form other self-aligned regions with the first region.

    摘要翻译： 在其他杂质区域内形成非常小的杂质区域而不需要提供临界掩模的方法。 在优选实施例中，这通过在衬底顶部的掩模层内形成底切带来限定第一杂质区域（例如双极晶体管的基极区域）来实现。 在通过引入杂质形成该区域之后，通过化学气相沉积工艺填充底切。 然后可以使用阻挡掩模来在第一区域内形成第二杂质区域，在这种情况下是发射极。 第二区域的窗口由填充带限定，从而确保所述第一和第二杂质区域的周边之间的选定距离。 也可以使用相同的掩模来与第一区域形成其它自对准区域。

    Process for preparing insulated gate semiconductor
    95.
    发明授权
    Process for preparing insulated gate semiconductor 失效
    制备绝缘栅半导体的工艺

    公开(公告)号：US4109371A

    公开(公告)日：1978-08-29

    申请号：US755943

    申请日：1976-12-30

    申请人： Hiroshi Shibata ,  Tsutomu Yoshihara

    发明人： Hiroshi Shibata ,  Tsutomu Yoshihara

    IPC分类号： H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  B01J17/00

    CPC分类号： H01L29/66575 ,  H01L21/033 ,  H01L21/28 ,  H01L29/0847

    摘要： An insulated gate semiconductor is prepared by forming auxiliary regions for source-drain regions having a shallow junction by a self-aligning process using a gate electrode as a mask; covering it with a thick insulating membrane for surface protection; forming a contact hole for bonding an electrode in the thick insulating membrane; and forming source-drain regions having deep junction through the contact hole and bonding an electrode metal to it in the contact hole.

    摘要翻译： 通过使用栅极电极作为掩模，通过自对准工艺形成具有浅结的源极 - 漏极区域的辅助区域来制备绝缘栅极半导体; 用厚的绝缘膜覆盖表面保护; 形成用于在所述厚绝缘膜中接合电极的接触孔; 以及形成具有通过所述接触孔的深接合的源极 - 漏极区域，并且将接触孔中的电极金属接合在其上。

    Method for fabricating self-aligned CCD devices and their output self-aligned MOS transistors on a single semiconductor substrate
    96.
    发明授权
    Method for fabricating self-aligned CCD devices and their output self-aligned MOS transistors on a single semiconductor substrate 失效
    在单个半导体衬底上制造自对准CCD器件及其输出自对准MOS晶体管的方法

    公开(公告)号：US4099317A

    公开(公告)日：1978-07-11

    申请号：US683361

    申请日：1976-05-05

    申请人： Stephen C. Su

    发明人： Stephen C. Su

    IPC分类号： H01L21/033 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/768 ,  B01J17/00

    CPC分类号： H01L29/66954 ,  H01L21/033 ,  H01L21/823406 ,  H01L29/76875

    摘要： The specification describes a self-aligning masking technique for the fabrication of charge coupled device-metal oxide semiconductor (CCD/MOS) transistor combinations. Both the CCD devices and the output MOS transistors are formed on the same semiconductor substrate during the same processing steps. Two layers of polycrystalline silicon, isolated from each other by a layer of dielectric material and isolated from the semiconductor substrate by another dielectric layer are used to form two sets of partially overlapping semiconductor strips. These strips and predetermined portions of the substrate are then doped, with a conductivity determining impurity opposite the conductivity type of the substrate. This process produces two self-aligned sets of gate electrodes for a two-phase or a four-phase CCD device and also produces two output self-aligned gate field effect transistors at the end of the CCD array.

    摘要翻译： 本说明书描述了用于制造电荷耦合器件 - 金属氧化物半导体（CCD / MOS）晶体管组合的自对准掩蔽技术。 在相同的处理步骤期间，CCD器件和输出MOS晶体管都形成在相同的半导体衬底上。 使用通过介电材料层彼此隔离并通过另一个介电层与半导体衬底隔离的两层多晶硅来形成两组部分重叠的半导体条。 然后将这些条和衬底的预定部分掺杂，其中电导率确定杂质与衬底的导电类型相反。 该过程为两相或四相CCD器件产生两个自对准的栅电极组，并且还在CCD阵列的末端产生两个输出自对准栅场效应晶体管。