公开(公告)号：US08039380B2

公开(公告)日：2011-10-18

申请号：US12163184

申请日：2008-06-27

申请人： Jean Dijon ,  Adeline Fournier

发明人： Jean Dijon ,  Adeline Fournier

IPC分类号： H01L21/20

CPC分类号： H01L21/76879 ,  B82Y30/00 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H05K3/4038 ,  Y10S977/70 ,  Y10S977/742 ,  Y10S977/855 ,  H01L2924/00

摘要： The present invention relates to a process for producing a carbon nanotube (CNT) mat on a conductive or semiconductor substrate. According to this process, a catalytic complex comprising at least one metal layer is firstly deposited on said substrate. Said metal layer then undergoes an oxidizing treatment. Finally, carbon nanotubes are grown from the metal layer thus oxidized. The present invention also relates to a process for producing a via using said CNT mat production process.

摘要翻译： 本发明涉及一种在导电或半导体衬底上制造碳纳米管（CNT）垫的方法。 根据该方法，首先将包含至少一个金属层的催化剂复合物沉积在所述基材上。 然后，所述金属层进行氧化处理。 最后，从被氧化的金属层生长碳纳米管。 本发明还涉及使用所述CNT垫制造方法制造通孔的方法。

公开(公告)号：US20110233779A1

公开(公告)日：2011-09-29

申请号：US13052367

申请日：2011-03-21

申请人： Makoto Wada ,  Yosuke Akimoto ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Noriaki Matsunaga ,  Tadashi Sakai ,  Naoshi Sakuma

发明人： Makoto Wada ,  Yosuke Akimoto ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Noriaki Matsunaga ,  Tadashi Sakai ,  Naoshi Sakuma

IPC分类号： H01L23/532 ,  H01L21/28 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L23/5226 ,  B82Y10/00 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes an interlayer insulation film provided on a substrate including a Cu wiring, a via hole formed in the interlayer insulation film on the Cu wiring, a first metal film selectively formed on the Cu wiring in the via hole, functioning as a barrier to the Cu wiring, and functioning as a promoter of carbon nanotube growth, a second metal film formed at least on the first metal film in the via hole, and functioning as a catalyst of the carbon nanotube growth, and carbon nanotubes buried in the via hole in which the first metal film and the second metal film are formed.

摘要翻译： 根据一个实施例，半导体器件包括设置在包括Cu布线的基板上的层间绝缘膜，形成在Cu布线上的层间绝缘膜中的通孔，选择性地形成在通孔中的Cu布线上的第一金属膜 作为Cu布线的屏障，起到碳纳米管生长的促进剂的功能，至少在通孔中的第一金属膜上形成的第二金属膜，并且用作碳纳米管生长的催化剂，碳 埋藏在其中形成有第一金属膜和第二金属膜的通孔中的纳米管。

公开(公告)号：US20110221044A1

公开(公告)日：2011-09-15

申请号：US12723532

申请日：2010-03-12

申请人： Michal Danek ,  Tom Mountsier ,  Jonathan Reid ,  Juwen Gao ,  Aaron Fellis

发明人： Michal Danek ,  Tom Mountsier ,  Jonathan Reid ,  Juwen Gao ,  Aaron Fellis

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described.

摘要翻译： 公开了用于在铜插塞和硅之间具有插入钨层的铜填充硅通孔（TSV）的装置和方法。 方法对于具有或不具有TSV特征的镶嵌处理是有用的。 钨层用作扩散阻挡层，用于铜电解填料的种子层和减少铜和硅之间CTE引起的应力的手段。 描述了钨层对硅和铜层与钨的粘附。

公开(公告)号：US07989222B2

公开(公告)日：2011-08-02

申请号：US12830510

申请日：2010-07-06

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L21/00

CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least two sublayers of oriented carbon nanotubes. A first sublayer is created by growing carbon nanotubes in a first direction parallel to the chip substrate from a catalyst in the presence of a reactant gas flow in the first direction, and a second sublayer is created by growing carbon nanotubes in a second direction parallel to the substrate and different from the first direction from a catalyst in the presence of a reactant gas flow in the second direction. The first and second directions are preferably substantially perpendicular. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal.

摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少两个定向碳纳米管的子层。 第一子层通过在第一方向上存在反应物气流的情况下从催化剂沿着平行于芯片基板的第一方向生长碳纳米管，并且通过沿与第一方向平行的第二方向生长碳纳米管来产生第二子层 在第二方向上存在反应气体流的情况下，不同于第一方向的催化剂。 第一和第二方向优选地基本垂直。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。

公开(公告)号：US07955972B2

公开(公告)日：2011-06-07

申请号：US12030645

申请日：2008-02-13

申请人： Lana Hiului Chan ,  Kaihan Ashtiani ,  Joshua Collins

发明人： Lana Hiului Chan ,  Kaihan Ashtiani ,  Joshua Collins

IPC分类号： H01L21/4763

CPC分类号： C23C16/0281 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76876 ,  H01L21/76877

摘要： The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 μΩ-cm for a 500 Angstrom film may be obtained.

摘要翻译： 本发明通过提供沉积具有高纵横比的小特征和特征的低电阻率钨膜的方法来满足这一需要。 这些方法包括通过脉冲成核层（PNL）工艺沉积非常薄的钨成核层，然后使用化学气相沉积（CVD）沉积钨层以填充该特征。 沉积钨成核层包括将基底暴露于含硼还原剂和含钨前体的交替脉冲，而不使用任何氢气，例如载体或背景气体。 使用该工艺，共形钨成核层可沉积至约10埃的厚度。 然后可以通过氢还原化学气相沉积工艺将特征全部或部分地填充钨。 对于500埃的膜可以获得约14μΩ·cm-cm的电阻率。

公开(公告)号：US20110104890A1

公开(公告)日：2011-05-05

申请号：US12935746

申请日：2009-07-14

申请人： Shoichiro Kumamoto ,  Masamichi Harada ,  Harunori Ushikawa

发明人： Shoichiro Kumamoto ,  Masamichi Harada ,  Harunori Ushikawa

IPC分类号： H01L21/768

CPC分类号： H01L21/76846 ,  C23C16/045 ,  C23C16/18 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76882

摘要： Provided is a Cu electrical interconnection film forming method, wherein an adhesive layer (base film) having improved adhesiveness with a Cu electrical interconnection film is used, in a semiconductor device manufacturing process. After forming a barrier film on a substrate whereupon a hole or the like is formed, a PVD-Co film or a CVD-Co film or an ALD-Co film is formed on the barrier film. Then, after filling up or burying the hole or the like, which has the Co film formed on the surface, with a CVD-Cu film or a PVD-Cu film, heat treatment is performed at a temperature of 350° C. or below, and the Cu electrical interconnection film is formed.

摘要翻译： 提供了一种Cu电互连膜形成方法，其中在半导体器件制造工艺中使用具有改善的与Cu电互连膜的粘合性的粘合剂层（基膜）。 在基板上形成阻挡膜之后，形成孔等，在阻挡膜上形成PVD-Co膜或CVD-Co膜或ALD-Co膜。 然后，在用CVD-Cu膜或PVD-Cu膜填充或埋入具有形成在表面上的Co膜的孔等之后，在350℃或更低的温度下进行热处理 ，形成Cu电互连膜。

公开(公告)号：US20110101528A1

公开(公告)日：2011-05-05

申请号：US12696276

申请日：2010-01-29

申请人： Yousuke Akimoto ,  Makoto Wada

发明人： Yousuke Akimoto ,  Makoto Wada

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/53276 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/76876 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S977/72 ,  H01L2924/00

摘要： A semiconductor device according to one embodiment includes: a substrate; a wiring provided above the substrate and including a graphene nanoribbon layer comprising a plurality of laminated graphene nanoribbon sheets; and a wiring connecting member penetrating at least one of the plurality of graphene nanoribbon sheets for connecting the wiring and a conductive member above or below the wiring.

摘要翻译： 根据一个实施例的半导体器件包括：衬底; 设置在所述基板上方并且包括石墨烯纳米纤维层的布线，所述石墨烯纳米纤维层包括多个层叠的石墨烯纳米薄片; 以及布线连接构件，其穿透所述多个石墨烯纳米纤维板中的至少一个，用于将所述布线连接到所述布线上方或下方的导电构件。

公开(公告)号：US20110014400A1

公开(公告)日：2011-01-20

申请号：US12651959

申请日：2010-01-04

申请人： Jing-Yi Huang ,  Laurence P. Sadwick

发明人： Jing-Yi Huang ,  Laurence P. Sadwick

IPC分类号： C23C16/44 ,  B05D1/36 ,  C23C14/14 ,  B05D3/00 ,  C23C14/34

CPC分类号： C03C17/40 ,  C03C17/36 ,  C03C17/3605 ,  C03C17/3615 ,  C23C14/025 ,  C23C14/165 ,  C23C14/185 ,  H01L21/2855 ,  H01L21/76838 ,  H01L21/76864 ,  H01L21/76876 ,  H01L2221/1078 ,  Y10T428/12576 ,  Y10T428/12611 ,  Y10T428/12743 ,  Y10T428/12875 ,  Y10T428/12889 ,  Y10T428/12903 ,  Y10T428/12944

摘要： A method of forming a structure useful in all forms of deposited metals, elemental metals, metal alloys, metal compounds, metal systems, including refractory metals such as tungsten and tantalum is provided. The structure generally comprises a substrate, a first layer formed atop the substrate, and a second layer formed atop the first layer. The first layer comprises a metal, which can be chromium, gold, platinum, aluminum, nickel, or copper. The second layer comprises a metal, elemental metal, metal alloy, metal compound, or metal system comprising a refractory metal such as tungsten or tantalum. The substrate can be a silicon, quartz or glass, metal, metal oxide or nitride.

摘要翻译： 提供一种形成可用于所有形式的沉积金属，元素金属，金属合金，金属化合物，金属体系，包括难熔金属如钨和钽的结构的方法。 该结构通常包括衬底，形成在衬底顶部的第一层和形成在第一层顶上的第二层。 第一层包括可以是铬，金，铂，铝，镍或铜的金属。 第二层包括金属，元素金属，金属合金，金属化合物或包含难熔金属如钨或钽的金属体系。 衬底可以是硅，石英或玻璃，金属，金属氧化物或氮化物。

公开(公告)号：US07863176B2

公开(公告)日：2011-01-04

申请号：US12119994

申请日：2008-05-13

申请人： Jaydeb Goswami ,  Allen McTeer

发明人： Jaydeb Goswami ,  Allen McTeer

IPC分类号： H01L23/52

CPC分类号： H01L23/5226 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench.

摘要翻译： 提供了用于在半导体器件中提供低电阻互连的装置和方法。 具体地，本发明的一个或多个实施例涉及将导电材料设置在沟槽中而不在导电材料和沟槽的侧壁之间设置电阻阻挡材料，使得导电材料占据沟槽的整个宽度。 例如，沟槽可以设置在由阻挡材料制成的一个或多个触点上，例如氮化钛也可以作为种子，并且导电材料可以在氮化钛的顶部生长以填充沟槽。

公开(公告)号：US07830016B2

公开(公告)日：2010-11-09

申请号：US12165176

申请日：2008-06-30

申请人： Mark Meldrim ,  Allen Mcteer ,  Alain P. Blosse

发明人： Mark Meldrim ,  Allen Mcteer ,  Alain P. Blosse

IPC分类号： H01L21/44

CPC分类号： H01L21/76876 ,  H01L21/2855 ,  H01L21/28556

摘要： Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.

摘要翻译： 简而言之，公开了一种包含β相钨晶种层的存储器件。